Imperial College London > Talks@ee.imperial > CAS Talks

CAS Talks

Add to your list(s) Send you e-mail reminders Further detail
Subscribe using ical/vcal (Help)

Talks organised by members of the Circuits and Systems Group.

Tell a friend about this list:

2 upcoming talks and 512 talks in the archive.

DiSCuS: Distributed Homomorphic Encryption on Edge Devices

UserAlexander Dalton (Imperial College).

HouseTeams (in the "CAS Seminars" team).

ClockMonday 29 November 2021, 16:00-17:00

Hyperblock Scheduling for a Verified High-Level Synthesis Tool

UserYann Herklotz Grave ( Imperial College).

HouseTeams (in the "CAS Seminars" team).

ClockMonday 22 November 2021, 16:00-17:00

Introduction to CXL

UserDan Iorga (Imperial College).

HouseTeams (in the "CAS Seminars" team).

ClockMonday 15 November 2021, 16:00-17:00

Title to be confirmed

UserDiederik Vink (Imperial College).

HouseTeams (in the "CAS Seminars" team).

ClockMonday 08 November 2021, 16:00-17:00

Resource Sharing for Verified High-Level Synthesis

UserMichalis Pardalos.

HouseTeams (in the "CAS Seminars" team).

ClockMonday 01 November 2021, 16:00-17:00

Egg: Efficient Equality Saturation for Rewriting Expressions

UserSam Coward (Imperial College).

HouseTeams (in the "CAS Seminars" team).

ClockMonday 12 July 2021, 16:00-17:00

Enabling Binary Neural Network Training on the Edge

UserErwei Wang (Imperial College).

HouseTeams (in the "CAS Seminars" team).

ClockMonday 28 June 2021, 16:00-17:00

Talk Postponed

UserGeorge A Constantinides (Imperial College).

HouseTeams (in the "CAS Seminars" team).

ClockMonday 24 May 2021, 16:00-17:00

Rapid RTL Prototyping (for Fun and Profit)

UserJames Davis (Imperial College).

HouseTeams (in the "CAS Seminars" team).

ClockMonday 17 May 2021, 16:00-17:00

Probabilistic Scheduling in High-Level Synthesis

UserJianyi Cheng (Imperial College).

HouseTeams (in the "CAS Seminars" team).

ClockMonday 26 April 2021, 16:00-17:00

Addressing DRAM Power Consumption in CNN Accelerators

UserAlexander Montgomerie-Corcoran (Imperial College).

HouseTeams (in the "CAS Seminars" team).

ClockMonday 15 March 2021, 16:00-17:00

On the Nature of Manual RTL Optimisations

UserTheo Drane (Intel).

HouseTeams.

ClockMonday 22 February 2021, 16:00-17:00

Introduction to Homomorphic Encryption and Its Applications

UserBen Chua.

HouseTeams.

ClockMonday 08 February 2021, 16:00-17:00

Title to be confirmed

UserJonathan R Beaumont (Imperial College).

HouseTeams.

ClockMonday 01 February 2021, 16:00-17:00

Approximate Logic Synthesis from Examples

UserSina Boroumand (Imperial College).

HouseTeams.

ClockMonday 25 January 2021, 16:00-17:00

Hardware Design and Verification with Cava

UserSatnam Singh (Google Research).

HouseTeams (in the "CAS Seminars" team).

ClockWednesday 20 January 2021, 16:00-17:00

Report from Internship at Samsung

UserAlexandros Kouris (Imperial College).

HouseTeams.

ClockMonday 18 January 2021, 16:00-17:00

Boolean Analysis

UserGeorge A Constantinides (Imperial College).

HouseTeams.

ClockMonday 18 January 2021, 10:00-11:00

Title to be confirmed

UserJiyu Fang (Imperial College).

HouseTeams.

ClockMonday 11 January 2021, 16:00-17:00

Homomorphic Encryption on Resource Constrained Devices

UserAlex Dalton.

HouseTeams.

ClockMonday 14 December 2020, 16:00-17:00

Formal Verification of High-Level Synthesis

UserYann Herklotz Grave ( Imperial College).

HouseTeams.

ClockMonday 07 December 2020, 16:00-17:00

Constructing non-linear Random Number Generators from iterated linear mappings

UserDavid B Thomas (Imperial College).

HouseTeams.

ClockMonday 30 November 2020, 16:00-17:00

The Semantics of Shared Memory in CPU/FPGA Systems

UserDan Iorga (Imperial College).

HouseTeams.

ClockMonday 23 November 2020, 16:00-17:00

Sparse and efficient deep neural network optimisation for embedded intelligence

UserJia Bi (Southampton).

HouseTeams.

ClockMonday 02 November 2020, 16:00-17:00

Memory Optimized Convolution Hardware Accelerator for Training (MOCHA-T)

UserDiederik Vink (Imperial College).

HouseTeams.

ClockMonday 12 October 2020, 16:00-17:00

Rethinking BNN Inference and Training on Embedded FPGAs

UserErwei Wang (Imperial College).

HouseTeams.

ClockTuesday 01 September 2020, 16:00-17:00

Precise pointer analysis in high-level synthesis

UserNadesh Ramanathan.

HouseTeams.

ClockMonday 10 August 2020, 16:00-17:00

Semiconductor Startups 2020, Back to the Future

UserPete Rodriguez, CEO, Silicon Catalyst.

HouseTeams.

ClockThursday 11 June 2020, 17:00-18:00

Predictable Accelerator Design with Time-Sensitive Affine Types

UserRachit Nigam (Cornell).

HouseTeams.

ClockMonday 08 June 2020, 16:00-17:00

Training Convolutional Neural Networks using Xilinx AI Engines

UserErwei Wang (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 27 April 2020, 16:00-17:00

Slow and Steady: Measuring and Tuning Multicore Interference

Practice Talk for RTAS

UserDan Iorga.

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 06 April 2020, 16:00-17:00

Efficient Video Recognition on Resource Constrained Mobile Devices

UserAmin Sabet (University of Southampton).

HouseLevel 9 Seminar Room, EEE Dept..

ClockThursday 13 February 2020, 10:00-11:00

Combining Dynamic & Static Scheduling in High-level Synthesis

UserJianyi Cheng (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 10 February 2020, 16:00-17:00

Finding and Understanding Bugs in FPGA Synthesis Tools

FPGA Practice Talk

UserYann Herklotz (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 03 February 2020, 16:00-17:00

Synchronous vs Asynchronous on POETS

UserJonathan R Beaumont (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 27 January 2020, 16:00-17:00

Tcling Quartus

UserJames Davis (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 20 January 2020, 16:00-17:00

Combining Dynamic & Static Scheduling in High-level Synthesis

UserJianyi Cheng (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 13 January 2020, 16:00-17:00

Global analysis of C Concurrency in High-level Synthesis

UserNadesh Ramanathan (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 09 December 2019, 16:00-17:00

Modeling Round-Off Error in the Fast Gradient Method for Predictive Control

UserIan McInerney (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 02 December 2019, 16:30-17:30

Analysis Methods for Memory in High-Level Synthesis

UserGeorge A Constantinides (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 02 December 2019, 16:00-16:30

Approximate Circuit Design Using Information Theory

UserSina Boroumand (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 25 November 2019, 16:00-17:00

Synthesis Without State Explosion -- from concurrent processes to netlists

UserDennis Fury (Plumstead Publishing).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 18 November 2019, 16:00-17:00

CANCELLED: Approximate Circuit Design Using Information Theory

UserSina Boroumand (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 14 October 2019, 16:00-17:00

Formalising isolation levels in SQL database transactions (tentative title)

UserMichail Pardalos, Imperial College London.

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 07 October 2019, 16:00-17:00

Energy Efficient VLSI Circuits for Machine Learning On-chip

UserHao Yu (Southern University of Science and Technology, China).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 30 September 2019, 16:00-17:00

Understanding memory consistency in CPU+FPGA devices

UserDan Iorga (Imperial).

HouseEEE Room 611.

ClockMonday 29 July 2019, 16:00-17:00

Fuzzing Verilog

UserYann Herklotz Grave, Imperial College.

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 01 July 2019, 16:00-17:00

The state-of-the-art in meta-learning and hyper-parameter optimization

UserDiederik Vink (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 17 June 2019, 16:00-17:00

Report back from FCCM 2019

UserErwei Wang (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 10 June 2019, 16:00-17:00

Dissipative Particle Dynamics using POETS technology

UserJonathan R Beaumont (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 03 June 2019, 16:00-17:00

Rethinking Deep Learning: Architectures and Algorithms

UserGeorge A Constantinides (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 20 May 2019, 16:00-17:00

CANCELLED: Learn Boolean Network using SAT to Design Approximate Circuits

UserSina Boroumand (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 13 May 2019, 16:00-17:00

Report on FPGA 2019

UserJianyi Cheng.

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 29 April 2019, 16:00-17:00

[FCCM'19 practice talk] LUTNet: Rethinking Inference in FPGA Soft Logic

Note unusual date

UserErwei Wang (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockThursday 25 April 2019, 16:00-17:00

[FCCM'19 practice talk] LUTNet: Rethinking Inference in FPGA Soft Logic

UserErwei Wang (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 15 April 2019, 16:00-17:00

CANCELLED: Approximate Arithmetic - A Hardware Perspective

UserGeorge A Constantinides (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 01 April 2019, 16:00-17:00

Modulo Scheduling in Electronic System Level Synthesis - Improving Performance and Control

Room changed

UserPatrick Sittel (U Kassel, Germany).

HouseDenis Gabor Seminar Room, 611.

ClockMonday 18 March 2019, 16:00-17:00

Less is more: graph partitioning for approximate circuit design

UserIlaria Scarabottolo (USI Lugano).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 11 March 2019, 16:00-17:00

Semantics of higher-order probabilistic programs

UserFredrik Dahlqvist (Imperial College London).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 04 March 2019, 16:00-17:00

Preserving Privacy through Processing Encrypted Data

UserMiriam Leeser (Northeastern University).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 11 February 2019, 16:00-17:00

EASY: Efficient Arbiter SYnthesis from Multi-threaded Code

UserJianyi Cheng (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 04 February 2019, 16:00-17:00

EASY: Efficient Arbiter SYnthesis from Multi-threaded Code

UserJianyi Cheng (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 28 January 2019, 16:00-17:00

No talk this week - no room available

UserSpeaker to be confirmed.

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 21 January 2019, 16:00-17:00

Speeding up HLS: Rational II modulo scheduling

Note unusual time

UserPatrick Sittel (visiting student from U Kassel, Germany).

HouseDenis Gabor Seminar Room, 611.

ClockWednesday 16 January 2019, 14:00-15:00

Modular SRAM-based Binary Content-Addressable Memories

UserAmeer Abdelhadi (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 14 January 2019, 16:00-17:00

Custom precision FPGA and GPU Multiple Precision Training (MuPT) in Caffe

UserDiederik Vink (Imperial College).

HouseDenis Gabor Seminar Room, 611.

ClockMonday 07 January 2019, 16:00-17:00

Multi-precision training for CNNs

UserAditya Rajagopal.

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 10 December 2018, 16:00-17:00

Project Trellis: enabling open source tools for the Lattice ECP5 FPGA

UserDavid Shah (Imperial College, Undergraduate).

HouseLevel 9 Seminar Room, EEE Dept.

ClockMonday 03 December 2018, 16:00-17:00

Analysis and Synthesis of Floating-Point Routines

UserZvonimir Rakamaric (University of Utah).

HouseDenis Gabor Seminar Room, 611.

ClockTuesday 27 November 2018, 16:00-17:00

An IP provider’s perspective on functional safety

UserVisiting Prof Pete Harrod (Arm).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 26 November 2018, 16:00-17:00

Asynchronous Systems - A world without time, part III

UserJonny Beaumont.

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 19 November 2018, 16:00-17:00

The Circuits and Systems Group

UserVarious.

HouseLevel 9 Seminar Room, EEE Dept.

ClockTuesday 30 October 2018, 09:30-11:30

Asynchronous Systems - A world without time, part II

UserJonny Beaumont.

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 22 October 2018, 16:00-17:00

From Custom CAD Tools to Circuit Reliability to IP Security: FPGA Research at BYU

UserBrent Nelson (Brigham Young University).

HouseLevel 9 Seminar Room, EEE Dept.

ClockMonday 15 October 2018, 16:00-17:00

Logic synthesis using SAT-solvers

UserSina Boroumand (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept.

ClockWednesday 10 October 2018, 16:30-17:30

POSTPONED

Room changed

UserSina Boroumand (Imperial College).

HouseMeeting room 1, Institute of Biomedical Engineering (IBE).

ClockMonday 08 October 2018, 16:00-17:00

A custom hardware architecture for state of the art Semi-dense mapping

UserKonstantinos Boikos (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 01 October 2018, 16:00-17:00

The E-method

UserMatei Valentin Istoan (Imperial College).

HouseRoom 610B, EEE Building.

ClockMonday 24 September 2018, 16:00-17:00

Computational Self-awareness for Cross-layer Resilience

UserNikil Dutt (UC Irvine).

HouseLevel 9 Seminar Room, EEE Dept..

ClockThursday 20 September 2018, 11:00-12:00

Various Arithmetic Talks

UserSpeaker to be confirmed.

HouseLevel 9 Seminar Room, EEE Dept.

ClockMonday 10 September 2018, 10:30-16:45

Asynchronous Systems - A world without time

UserJonny Beaumont.

HouseEEE Department, Room 503.

ClockMonday 03 September 2018, 16:00-17:00

What’s happening in programming languages research?

UserJohn Wickerson (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 23 July 2018, 16:00-17:00

Automated Full-Stack Memory Model Verification with the Check suite

Note unusual date

UserYatin Manerkar (Princeton).

HouseLevel 9 Seminar Room, EEE Dept..

ClockThursday 12 July 2018, 14:00-15:00

How to Write

UserJames Davis (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 09 July 2018, 16:00-17:00

LUT-based BNN: Forward Propagation with Arbitrary Binary Operations

UserErwei Wang (Imperial College).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 02 July 2018, 16:00-17:00

f-CNNx: Deploying Multiple CNNs in Complex AI Systems

UserStelios I. Venieris (Imperial College London).

HouseLevel 9 Seminar Room, EEE Dept..

ClockMonday 25 June 2018, 16:00-17:00

Injecting many FPGA configuration faults

UserShane Fleming (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 14 May 2018, 16:00-17:00

FCCM Practice: Concurrency-Aware Thread Scheduling for High-Level Synthesis

UserNadesh Ramanathan (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 16 April 2018, 16:00-17:00

Online Algorithms and the E-Method on FPGAs

UserMatei Valentin Istoan (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 26 March 2018, 16:00-17:00

Online Algorithms and the E-Method on FPGAs

UserSpeaker to be confirmed.

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 26 March 2018, 16:00-17:00

Black-box approximation of bivariate functions

UserDavid B Thomas (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 19 February 2018, 16:00-17:00

The state of the art in SLAM and why FPGA-SoCs can play an important role

UserKonstantinos Boikos (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 29 January 2018, 16:00-17:00

How to prove a theorem using the Isabelle Proof Assistant

UserJohn Wickerson (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 22 January 2018, 16:00-17:00

CNN-to-FPGA Toolflows: An Overview and Future Directions

UserStelios I. Venieris (Imperial College London).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 15 January 2018, 16:00-17:00

Using the Intel HARP2 System - A Tutorial

UserFelix Winterstein (Imperial College).

HouseDepartment of Electrical and Electronic Engineering, Room 503.

ClockThursday 11 January 2018, 11:00-13:00

Acceleration of Top-k ListNet Training Using FPGA

UserQiang (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 18 December 2017, 15:00-16:00

Emergent Synchronisation on the POETS Architecture

UserShane Fleming (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 20 November 2017, 15:00-16:00

The PRiME Framework: Application- and Platform-agnostic Runtime Management

UserJames Davis (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 13 November 2017, 15:00-16:00

Title to be confirmed

UserKonstantinos Boikos (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 30 October 2017, 15:00-16:00

Title to be confirmed

UserMatei Valentin Istoan (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 23 October 2017, 15:00-16:00

A Method for Computing Sine and Cosine on FPGAs

UserMatei Valentin Istoan (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 23 October 2017, 15:00-16:00

Compiling OP2 into events, and beyond!!! Maybe...

UserDavid B Thomas (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 02 October 2017, 15:00-16:00

Title to be confirmed

UserJohn Wickerson (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 25 September 2017, 15:00-16:00

A Framework for Mapping Multiple Convolutional Neural Networks on FPGAs

UserStelios I. Venieris (Imperial College London).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 18 September 2017, 15:00-16:00

Scheduling weakly consistency C concurrency for reconfigurable hardware

UserNadesh Ramanathan (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 11 September 2017, 15:00-16:00

POETS : partially ordered event triggered systems

UserDavid B Thomas (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 03 July 2017, 15:00-16:00

Streaming Abstractions for FPGA High Level Synthesis

UserJohn McAllister (Queen's University Belfast).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 03 July 2017, 14:00-15:00

Tile Size Selection for Optimized Memory Reuse in High-Level Synthesis

UserJunyi Liu ().

House503.

ClockMonday 19 June 2017, 15:00-16:00

Shared Virtual Memory in Heterogeneous Systems

UserFelix Winterstein (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 12 June 2017, 15:00-16:00

Program Slicing for High-level synthesis

UserShane Fleming (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 15 May 2017, 15:00-16:00

Input-dependent Static Timing Analysis (iSTA)

UserAndrea Suardi (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 08 May 2017, 15:00-16:00

Adventures in Signal Selection

UserJames Davis (Imperial College).

HouseLevel 9 Seminar Room, EE Dept..

ClockMonday 27 March 2017, 15:00-16:00

A High-Performance System-on-Chip Architecture for Direct Tracking and SLAM

UserKonstantinos Boikos (Imperial College).

HouseRoom 610B, EEE Building.

ClockMonday 06 March 2017, 15:00-16:00

Automatically Comparing Memory Consistency Models

UserJohn Wickerson (Imperial College).

HouseRoom 610B, EEE Building.

ClockMonday 13 February 2017, 15:00-16:00

Hardware Synthesis of Weakly Consistent C Concurrency

UserNadesh Ramanathan (Imperial College).

HouseIBE Meeting Room 1.

ClockMonday 06 February 2017, 15:00-16:00

fpgaConvNet: Automated Design Space Exploration for FPGA-based Convolutional Neural Networks

UserStelios I. Venieris (Imperial College London).

HouseRoom 610B, EEE Building.

ClockMonday 23 January 2017, 15:00-16:00

A look into the Intel FPGA SDK for OpenCL

UserJoshua M Levine (Imperial College).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockMonday 12 December 2016, 15:00-16:00

TALK POSTPONED - NO TALK THIS WEEK

UserJoshua M Levine (Imperial College).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockMonday 05 December 2016, 15:00-16:00

An Efficient Implementation of Online Arithmetic

UserAaron Zhao (Former BEng Student at Imperial, now MPhil Student at Cambridge).

House144 Huxley Building, DoC.

ClockMonday 21 November 2016, 15:00-16:00

HiPEDS Seminar - Automatically Comparing Memory Consistency Models

UserDr John Wickerson, EEED.

House144 Huxley Building, DoC.

ClockWednesday 26 October 2016, 12:00-13:00

Power to the People

UserJames Davis (Imperial College).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockMonday 10 October 2016, 15:00-16:00

Title to be confirmed

UserQiang Li (Imperial College).

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockMonday 05 September 2016, 15:00-16:00

Automatically Comparing Memory Consistency Models

UserJohn Wickerson (Imperial College).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockMonday 15 August 2016, 15:00-16:00

FPL2016 Practice Talk

UserKonstantinos Boikos (Imperial College).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockTuesday 19 July 2016, 14:00-15:00

Large Scale Configurable Clouds

UserDoug Burger (Microsoft).

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockFriday 27 May 2016, 11:00-12:00

FCCM 2016 - Debrief

UserSpeaker to be confirmed.

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockMonday 16 May 2016, 13:00-14:00

FCCM 2016 - Practice Talks

UserSpeaker to be confirmed.

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockWednesday 27 April 2016, 16:00-18:00

FPGAs in the Datacenter at Microsoft

UserAaron Smith (Microsoft).

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockMonday 21 March 2016, 14:00-15:00

ARC 2016 - Practice Talk

UserMarlon Wijeyasinghe.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 17 March 2016, 10:00-11:00

FPGA 2016 - Debrief

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 14 March 2016, 15:00-16:00

FPGA 2016 - Practice Talks

UserXitong Gao and Nadesh Ramanathan.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 11 February 2016, 14:00-15:00

Better Pipelining in High-level Synthesis

UserJunyi Liu.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 18 January 2016, 15:00-16:00

Custom-Sized Caches in Application-Specific Memory Hierarchies (FPT practice talk)

UserFelix Winterstein (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 02 December 2015, 15:00-16:00

Using an FPGA SoC to accelerate semi-dense embedded SLAM applications

UserKonstantinos Boikos (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 09 November 2015, 15:00-16:00

Title to be confirmed

UserLiucheng Guo (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 26 October 2015, 15:00-16:00

Heterogeneous Multi-Processor Pipelines: a Real-Time MPSoC Story

UserSri Parameswaran (University of New South Wales).

HouseDenis Gabor Seminar Room, 611.

ClockFriday 23 October 2015, 11:00-12:00

Accelerating Non-Linear SVM Training on FPGAs

UserMudhar Bin Rabieah (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 19 October 2015, 15:00-16:00

The logic of MOSFET logic

UserDan Ghica (University of Birmingham).

HouseEEE Department, Room 503.

ClockFriday 09 October 2015, 11:30-12:30

An Exact MCMC Accelerator Under Custom Precision Regimes

UserShuanglong Liu (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 05 October 2015, 14:00-15:00

StitchUp: Protecting the Control-Flow of HLS Circuits Through Program Slicing

UserShane Fleming (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 28 September 2015, 14:00-15:00

Title to be confirmed

UserAndrea Suardi (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 21 September 2015, 14:00-15:00

Title to be confirmed

UserXitong Gao (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 14 September 2015, 14:00-15:00

FPL practice talk

UserStelios I. Venieris (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 28 August 2015, 14:00-15:00

FPL practice talk

UserHilda Xue (CAS).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 24 August 2015, 11:30-12:30

Bending Quartus II to Your Will!

UserJoshua M Levine (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 20 July 2015, 11:30-12:30

Design of Approximate Overclocked Datapath

UserKan Shi (Imperial College).

HouseDennis Gabor Seminar Room 611, EE Dept..

ClockMonday 13 July 2015, 11:30-12:30

From C to FPGA proptotype with TCL scripts

UserAndrea Suardi (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 29 June 2015, 11:30-12:30

Low Overhead Mitigation of Radiation Effects in SRAM-Based FPGAs for Avionics

UserMichail Vavouras (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 15 June 2015, 11:30-12:30

The CProver Program Analysis Tools

UserOxford.

HouseEEE Department, Room 503.

ClockTuesday 02 June 2015, 11:00-12:00

Computing in the Deep

UserStelios Venieris.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 01 June 2015, 11:30-12:30

OpenCL for FPGAs

UserGordon Inggs (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 11 May 2015, 11:30-12:30

FCCM '15 practice talk

UserLiucheng Guo (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 31 March 2015, 13:00-14:00

Particle MCMC acceleration for large-scale inference in genetics using FPGAs

UserGrigorios Mingas (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 30 March 2015, 11:30-12:30

FPGA'15 debrief

UserMultiple speakers.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 19 March 2015, 14:00-15:00

MATCHUP: Memory Abstractions for Heap Manipulating Programs - FPGA'15 Practice Talk

UserFelix Winterstein (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 19 February 2015, 11:00-12:00

Delay-Bounded Routing for Shadow Registers (dry-run for FPGA15)

UserEddie Hung (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 12 February 2015, 14:30-15:30

CypherDB: A Novel Architecture for Outsourcing Secure Database Processing

UserHung Chen (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 09 February 2015, 11:30-12:30

FPT '14 debrief

UserMultiple speakers.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 26 January 2015, 11:30-12:30

Bridging the gap between networking and end-host computing

UserNoa Zilberman (University of Cambridge).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 19 January 2015, 11:30-12:30

Title to be confirmed

UserOghenevworhe Joan Omeru (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 08 December 2014, 11:30-12:30

FPT '14 practice talk (Part 2)

UserShuanglong Liu and Aryan Tavakkoli (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 04 December 2014, 10:00-11:30

Loop Pipelining in High-level Synthesis

UserJunyi Liu (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 01 December 2014, 11:30-12:30

FPT '14 practice

UserGordon Iggs, Kan Shi, Shuanglong Liu.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 25 November 2014, 09:00-11:15

High-level synthesis of stochastic circuits

UserJason Anderson.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 24 November 2014, 11:30-12:30

New Applications of Moment-SOS hierarchies

UserVictor Magron (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 17 November 2014, 11:30-12:30

Low-latency option pricing using systolic binomial trees

UserAryan Tavakkoli (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 03 November 2014, 11:30-12:30

Title to be confirmed

UserEdward A Stott (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 29 September 2014, 11:00-12:00

Robust explicit MPC design under finite precision arithmetic

UserAndrea Suardi (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 22 September 2014, 11:00-12:00

FPL 2014 debrief

UserMultiple speakers.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 15 September 2014, 11:00-12:00

Automated Framework for FPGA-Based Parallel Genetic Algorithms

UserLiucheng Guo (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 25 August 2014, 11:00-12:00

A Scalable approach for Data Assimilation methods

UserRossella Arcucci.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 21 July 2014, 11:00-12:00

Accelerating Finite Element Methods on FPGA

UserPavel Burovskiy (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 14 July 2014, 11:00-12:00

Practical Techniques for Auto-Active Verification

UserNadia Polikarpova.

HouseRoom 217, Department of Computing.

ClockTuesday 08 July 2014, 11:00-12:00

DAC '14 debrief

UserKan Shi (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 30 June 2014, 11:00-12:00

To Infinity... and Beyond!

UserGeorge A Constantinides (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 16 June 2014, 11:00-12:00

Templates and Higher Level Synthesis

UserPeter Ogden (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 09 June 2014, 11:00-12:00

Parallel resampling for Particle Filters on FPGAs

UserShuanglong Liu (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 02 June 2014, 11:00-12:00

DAC14 practice talk

UserKan Shi (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 30 May 2014, 13:30-14:30

FCCM '14 debrief

UserJoshua M Levine (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 23 May 2014, 14:00-15:00

OPS-SAT: How will commercial FPGAs cope in space?

UserShane Fleming and Felix Winterstein (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 07 May 2014, 11:00-12:00

How Often Is Floating-Point Addition Non-Associative?

UserTheo Drane (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 07 March 2014, 16:00-17:00

Zero Overhead FPGA Instrumentation

UserEddie Hung (Imperial College).

HouseLevel 11 Control Seminar room, room 1109a, EE Dept..

ClockTuesday 04 March 2014, 12:00-13:00

"PEACH2: an FPGA switching fabric for high performance computing"

UserTakaaki Miyajima (Miya).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 21 February 2014, 16:00-17:00

FPGA '14 practice talk

UserJoshua M Levine (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 20 February 2014, 13:00-14:00

Timing Fault Detection in FPGAs

UserEdward A Stott (Imperial College).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockWednesday 29 January 2014, 11:00-12:00

The Many Lives of an FPGA DSP Block

UserSuhaib Fahmy (Nanyang Technological University).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockWednesday 08 January 2014, 15:00-16:00

CAS IT presentation

UserGordon Inggs (Imperial College).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockThursday 05 December 2013, 14:00-15:00

Balancing Higher-Order Convergence and Architectural Efficiency for Finite-Difference Methods

UserOghenevworhe Joan Omeru (Imperial College).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockWednesday 13 November 2013, 11:00-12:00

Practical skills for digital electronics researchers : useful software glue

UserSamuel Bayliss (Imperial College).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockWednesday 16 October 2013, 11:00-12:00

Optical Communications Overview and FPGA-based DSP

UserChristos Spatharakis (Photonics Communications Research Lab - NTUA Athens).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 15 October 2013, 15:00-16:00

Optical Communications Overview and FPGA-based DSP

UserChristos Spatharakis, Photonics Communications Research Lab at NTUA, Athens.

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockTuesday 15 October 2013, 15:00-16:00

A polynomial time algorithm for word-length optimisation

UserKarthick Parashar (Impeial College, CAS).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockWednesday 25 September 2013, 14:00-15:00

FPL 2013 Debrief Session

UserMultiple speakers.

HouseRoom 503, EEE Department.

ClockThursday 12 September 2013, 14:00-15:00

The Case for Embedded NoCs on FPGAs

UserVaughn Betz, University of Toronto.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 30 August 2013, 11:00-12:00

FPL practice talk

UserFelix Winterstein (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 14 August 2013, 12:30-13:30

Progressive sampling of image data in hardware systems

UserJianxiong Liu (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 10 July 2013, 11:00-12:00

Energy Efficient Computing System - Research in NICS CAD Tsinghua

UserYu Wang (Tsinghua University, China).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 09 July 2013, 11:00-12:00

Toward accurate polynomial evaluation in rounded arithmetic

UserTheo Drane (Imperial College).

HouseRoom 610B, EEE Department.

ClockFriday 28 June 2013, 11:00-12:00

Making Heterogeneous Computing Accessible

UserGordon Inggs (CAS, Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 19 June 2013, 11:00-12:00

FCCM '13 Debrief

UserMultiple speakers.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 17 May 2013, 11:00-12:00

ISCAS Practce Talk

UserKan Shi (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 14 May 2013, 11:00-12:00

FPGA fast prototyping with LabVIEW and Vivado HLS

UserAndrea Suardi and Felix Winterstein (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 14 May 2013, 10:00-11:00

Accelerating the training process of Random Forest classifier on FPGA

UserChuan Cheng (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 01 May 2013, 11:00-12:00

Per-path Physical Timing analysis tool for arbitrary circuits on FPGA

UserJustin Wong (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 24 April 2013, 11:00-12:00

FCCM practice talks

UserMultiple speakers.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 22 April 2013, 10:00-13:00

FCCM practice

UserGrigorios Mingas (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 17 April 2013, 11:00-12:00

BERI - an open source 64-bit processor for multicore research

UserSimon Moore (Cambridge).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 27 March 2013, 11:00-12:00

Real-Time Image Processing with Catapult-C

UserRui Duarte (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 13 March 2013, 11:00-12:00

ARC practice: Fast matrix multiplication over small finite fields

UserShane Fleming (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 12 March 2013, 10:00-11:00

Git: Introduction and Tutorial

UserPeter Ogden (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 27 February 2013, 11:00-12:00

Co-design of embedded MPC controllers

UserAndrea Suardi (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 20 February 2013, 11:00-12:00

A Joint Framework for Face Super-Resolution

UserYonggang Jin (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 06 February 2013, 11:00-12:00

The Arts and Crafts of Quartus II

UserJoshua M Levine (Imperial College).

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockWednesday 12 December 2012, 11:00-12:00

Highlights from ICCAD 2012: Where's the Tofu?

UserSamuel Bayliss (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 05 December 2012, 11:00-12:00

Optimal Control of an Atomic Force Microscope on an FPGA using the Fast Gradient Method

UserJuan Jerez Fullana (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 28 November 2012, 11:00-12:00

Optimizing the arithmetic precision of MCMC algorithms

UserGrigorios Mingas (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 21 November 2012, 11:00-12:00

EDA Club Open Day: FMCAD for CAS

UserDavid P Boland (Imperial College).

HouseRoom 610B, EEE Department.

ClockThursday 15 November 2012, 15:00-16:00

Some approaches to the static analysis of programs

UserDavid Monniaux (VERIMAG).

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockWednesday 14 November 2012, 11:00-12:00

Multi-level Monte Carlo Simulation with Mixed Floating-point Precision

UserZhiyong Liu (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 08 November 2012, 11:00-12:00

Using Training Statistics for Prediction Adjustment in Regression Forests

UserAdam Powell (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 07 November 2012, 11:00-12:00

Float to Float Function Approximation

UserDavid B Thomas (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 31 October 2012, 11:00-12:00

Some Experiments in Scala

UserGeorge A Constantinides (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 19 October 2012, 11:00-12:00

Error-tolerant software adaptation of signal processing systems

UserYiannis Andreopoulos.

HouseRoom 503, Level 5, EEE Dept. .

ClockThursday 18 October 2012, 16:00-17:00

System-level approaches for fixed-point refinement of signal processing algorithms

UserKarthick Parashar (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 10 October 2012, 11:00-12:00

Theo's Toolkit Wishlist

UserTheo Drane (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 04 October 2012, 11:00-12:00

Overclocking Datapath for Latency-Error Tradeoff

UserKan Shi (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 13 September 2012, 13:00-14:00

FPL 2012 Debrief

UserNachiket Kapre.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 10 September 2012, 13:00-14:00

Atlantica 2012 - Talk 7 - RIFFA

UserFarhan Rahman.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 05 September 2012, 18:00-18:15

Atlantica 2012 - Talk 6 - Lanczos++

UserAbid Rafique.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 05 September 2012, 17:00-17:45

Atlantica 2012 - Talk 5 - SAT Solvers

UserAndrew Bean.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 05 September 2012, 16:15-17:00

Atlantica 2012 - Talk 4 - Matrix-Free SPICE

UserCoryan Wilson-Shah.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 05 September 2012, 15:30-16:15

Atlantica 2012 - Talk 1 - AutoESL Graph Machine Mapping

UserGordon Inggs (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 05 September 2012, 11:00-11:45

Reduced Complexity Tone Classifier for Automatic Tonal Speech Recognizer

UserJirabhorn Chaiwongsai (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 30 August 2012, 13:00-14:00

Hardware Assisted Security in Cloud Computing

UserHung Chen (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 29 August 2012, 11:00-12:00

FPL practice talk #2

UserAbid Rafique (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 24 August 2012, 15:00-16:00

Graph Machine Practice Talk

UserGordon Inggs.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 24 August 2012, 14:00-15:00

Software for Research - Day 4 - Signal Processing

UserDr. Eduardo Aguilar Pelaez (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 24 August 2012, 11:00-12:00

Software For Research - Day 3 - Compute Cluster Management

UserImperial College London.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 23 August 2012, 14:00-15:00

Software for Research - Day 2 - C++ STL

UserPeter Ogden.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 22 August 2012, 11:00-12:00

Software for Research - Day 1 - Result Analytics

UserAndrew Bean and Zhenyu Guan.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 21 August 2012, 11:00-12:00

Enhancing Performance of Tall-Skinny QR Factorization using FPGAs

UserAbid Rafique (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 16 August 2012, 13:00-14:00

Title to be confirmed

UserAndrew Bean (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 09 August 2012, 13:00-14:00

Beyond worst-case clocking of circuits

UserEdward A Stott (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 19 July 2012, 13:00-14:00

YAIOCM - Yet another invitation-only coding marathon

UserNachiket Kapre (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 13 July 2012, 11:00-17:00

vfscaling coding 10k run (invitation-only)

UserNachiket Kapre (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 12 July 2012, 13:00-17:00

Coding Marathon #4

UserNachiket Kapre.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 06 July 2012, 11:00-17:00

Coding Marathon #3 (Reuse old invitation)

UserNachiket Kapre.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 29 June 2012, 11:00-17:00

Coding Marathon #2 (Reuse old Invitation)

UserNachiket Kapre.

HouseEEE610B.

ClockFriday 22 June 2012, 12:00-17:00

Transfer presentation

UserRui Duarte (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 20 June 2012, 15:30-16:00

Coding Marathon (Invitation-Only)

UserNachiket Kapre (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 15 June 2012, 11:00-17:00

Context-based vision processing system

UserJianxiong Liu (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 14 June 2012, 13:00-14:00

DeSyRe - On Demand System Reliability

UserMichail Vavouras (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 07 June 2012, 13:00-14:00

Monte Carlo Simulation On FPGA Implementation

UserZhiyong Liu (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 31 May 2012, 13:00-14:00

Software Engineering Best Practices for High-Impact Research

UserPeter Ogden (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 25 May 2012, 11:00-12:00

Optimal Hardware Implementation of an Optimal Controller

UserAndrea Suardi (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 24 May 2012, 13:00-14:00

Greener Search: FPGA Acceleration of Real-time Unstructured Search

UserWim Vanderbauwhede, University of Glasgow.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 23 May 2012, 11:00-12:00

Integer Point Counting Techniques for Polyhedra

UserSamuel Bayliss (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 17 May 2012, 13:00-14:00

FCCM practice

UserJuan Jerez Fullana & Grigorios Mingas (Imperial College London) .

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 25 April 2012, 16:00-17:00

OpenCPI/SCORE Progress Meeting

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 23 April 2012, 17:00-18:00

Helene's FCCM 2012 Practice

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 20 April 2012, 17:00-18:00

Nachiket's Group Meeting

UserNachiket Kapre (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 13 April 2012, 12:30-13:30

Lanczos on FPGA - ARC Talk Take #2

UserAbid Rafique.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 03 April 2012, 11:00-12:00

FPGA CONNECT NoC generator

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 29 March 2012, 18:30-19:30

System Optimization Techniques for Hardware Compiler

UserDr. Sujit Bhattacharya (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 29 March 2012, 13:00-14:00

Assorted student talks

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 28 March 2012, 11:00-15:00

Courier: A Domain Specific Language and Toolchain for Runtime Binary Acceleration

UserTakaaki Miyajima, Keio University, Japan.

HouseMahanakorn Conference room, level 9.

ClockFriday 23 March 2012, 13:00-14:00

An Efficient FPGA-based Design for Programmable Ion Channel Simulations

UserGraeme Coapes (Newcastle University).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 22 March 2012, 13:00-14:00

ASPLOS/FPGA 2012 Debrief

UserNachiket Kapre.

HouseDenis Gabor Seminar Room, 611.

ClockFriday 16 March 2012, 13:00-14:00

Face Super-Resolution

UserYonggang Jin (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 15 March 2012, 13:00-14:00

ARC '12 practice

UserGrigoris Mingas & Abid Rafique (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 08 March 2012, 13:00-14:00

Performance Prediction of Image Compression Methods on Soft Processors

UserAdam Powell (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 01 March 2012, 13:00-14:00

FPGA 2012 Practice

UserNikil Mehta.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 20 February 2012, 15:30-16:30

CAS Seminar on FPGA Variability, and Architecture (Guest speaker from Japan)

UserJustin Wong, Zhenyu Guan (Imperial College) and Dr. Kazuya Tanigawa (Hiroshima City University, Japan).

HouseEEE Room 611 (Gabor Seminar Room).

ClockThursday 16 February 2012, 11:00-13:30

Increasing the efficiency and accessibility of next-generation computing platforms

UserLesley Shannon (Simon Fraser University).

HouseRoom 503, EE Dept..

ClockTuesday 14 February 2012, 16:00-17:00

NTU Seminar Practice #2

UserNachiket Kapre (Imperial College).

HouseHuxley 218.

ClockThursday 09 February 2012, 17:00-18:00

Mesh NoCs with Bluespec

UserBlithe.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 02 February 2012, 14:30-15:30

NTU Seminar Practice #1

UserNachiket Kapre (Imperial College).

HouseEEE Room 611.

ClockThursday 02 February 2012, 11:00-12:00

'Sharpening the Ax' - development of the Rhino System

UserGordon Inggs (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 26 January 2012, 13:00-14:00

Title to be confirmed

UserTheo Drane (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 19 January 2012, 13:00-14:00

FPT 2011 Debrief

UserNachiket Kapre (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 16 January 2012, 11:00-12:00

Feasibility of accelerating random forest using FPGA

UserChuan Cheng (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 12 January 2012, 13:00-14:00

Asynchronous circuits for High-performance Energy Minimum Operation

UserBen Devlin, University of Tokyo.

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockFriday 09 December 2011, 13:00-14:00

A Reliability Carol: Detecting the Ghost of Errors Past, Present and Future

UserJoshua M Levine (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 08 December 2011, 13:00-14:00

Sparse Matrix-Solve Unroll

UserSiddhartha.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 05 December 2011, 13:00-13:15

Dummy

UserAbid Rafique (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 05 December 2011, 12:15-13:00

VLIW-SCORE (FPT 2011 2nd practice)

UserNachiket Kapre (Imperial College).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockMonday 05 December 2011, 11:00-12:00

Approaching the Peak GPU Performance in FPGAs for Scientific Computing

UserJuan Jerez Fullana (Imperial College London).

HouseRoom 503, EE Dept..

ClockFriday 25 November 2011, 12:00-13:00

VLIW-SCORE (FPT2011 Raw Practice)

UserNachiket Kapre (Imperial College).

HouseLevel 9 Mahanakorn Lab., EEE Dept..

ClockFriday 25 November 2011, 11:00-12:00

FPT'11 Practice Talk (Timing Speculation in FPGAs: Probabilistic Inference of Data Dependent Failure Rates)

UserSumanta Chaudhuri and Justin Wong (Imperial College).

HouseRoom 503, EE Dept..

ClockThursday 24 November 2011, 12:00-13:00

A reliability-aware design methodology for embedded systems on multi-FPGA platforms

UserChiara Sandionigi (Politecnico di Milano).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 14 November 2011, 14:00-15:00

The VENICE Soft Vector Processor

UserGuy Lemieux (UBC).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 14 November 2011, 11:00-12:00

OpenCPI - an open source framework for component-based development in heterogeneous processing embedded systems

UserJames Kulp, Parera Information Services and Shepard Siegel, Atomic Rules.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 11 November 2011, 16:00-17:00

Fixed Point Refinement: A systems approach

UserKarthick Parashar (IRISA).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 01 November 2011, 14:00-15:00

Optimization through GPGPUs

UserGabriel Caffarena (University CEU San Pablo).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 28 October 2011, 11:00-12:00

FPGA implementation of Parallel Tempering MCMC

UserGrigoris Mingas (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 27 October 2011, 13:00-14:00

Designing optimal digital hardware using the Polytope Model

UserSamuel Bayliss (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 20 October 2011, 13:00-14:00

Fixed-point explicit MPC in FPGAs

UserAndrea Suardi (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 13 October 2011, 13:00-14:00

FPL '11 Debrief

UserEdward A Stott (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 13 September 2011, 10:00-11:00

Computing with Streams in SCORE

UserNachiket Kapre (Imperial College).

HouseRoom 503/EEE.

ClockFriday 09 September 2011, 11:00-13:00

Imperial-Penn Series: MSc Student Project Presentations

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 06 September 2011, 14:00-16:00

Title to be confirmed

UserRui Duarte (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 30 August 2011, 10:00-11:00

OpenCPI Experiences for ML605 Board

UserUdit and Albert.

HouseRoom 503/EEE.

ClockFriday 19 August 2011, 14:00-15:00

Can you quote the b-Ax norm as a measure of how well you solved Ax=b?

UserDavid P Boland and Bianca Furtuna (Imperial College) .

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 19 August 2011, 10:00-11:00

Imperial-Penn Group Meeting

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 16 August 2011, 16:00-18:00

Visual memory aided image enhancement

UserJianxiong Liu (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 02 August 2011, 10:00-11:00

Imperial-Penn Group Meeting

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 26 July 2011, 16:00-17:00

FPGA implementation of Viola&Jones face detector with dynamic workload balancing

UserChuan Cheng (Imperial College London).

HouseRoom 503/EEE.

ClockTuesday 26 July 2011, 10:00-11:00

Imperial CAS Reading Group

UserJosh Levine and Nachiket Kapre.

HouseRoom 503/EEE.

ClockFriday 22 July 2011, 12:00-13:00

GraphStep: Compute Model and Programming Tutorial

UserNachiket Kapre (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 15 July 2011, 13:00-15:00

Nachiket's MSc Student Talks (Continued)

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 12 July 2011, 13:00-14:00

Multiprocessor Scheduling, Resource Allocation and Numerical Data Representation

UserSujit Bhattacharya (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 12 July 2011, 10:00-11:00

Imperial CAS Reading Group

UserAlex Casson and Theo Drane.

HouseRoom 503/EEE.

ClockFriday 08 July 2011, 12:00-13:30

Nachiket's MSc Student Group Presentation #2

UserHelene Martorell, Emmanouil Spanakis, Fang Zhou and Wei Lizhong.

HouseRoom 503.

ClockMonday 04 July 2011, 13:00-15:00

ISCA/PLDI Debrief

UserNachiket Kapre.

HouseRoom 503/EEE.

ClockFriday 01 July 2011, 15:00-16:00

Imperial-Penn Group Meeting

UserRafi Rubin and Zhenyu Guan.

HouseRoom 503/EEE.

ClockTuesday 28 June 2011, 16:00-18:00

A Run-time Adaptive FPGA Architecture for Monte Carlo Simulations

UserXiang Tian (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 28 June 2011, 10:00-11:00

Smartphone Power Amplifier Circuit Design

UserKasra Omid-Zohoor, PhD student at Stanford University.

HouseGabor lecture room, 611 EE Dept..

ClockThursday 23 June 2011, 14:00-15:00

Title to be confirmed

UserTheo Drane (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 21 June 2011, 10:00-11:00

A Sparse and Condensed QP Formulation for Predictive Control

UserJuan Jerez Fullana (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 07 June 2011, 10:00-11:00

Imperial CAS Reading Group

UserSpeaker to be confirmed.

HouseRoom 503/EEE.

ClockTuesday 31 May 2011, 12:00-13:00

Imperial-Penn Group Meeting

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 24 May 2011, 16:00-18:00

Explicit Model Predictive Control in FPGAs

UserAndrea Suardi (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 24 May 2011, 10:00-11:00

Imperial CAS Reading Group

UserSpeaker to be confirmed.

HouseRoom 503/EEE.

ClockWednesday 18 May 2011, 14:00-15:00

SPICE Next Steps

UserNachiket Kapre (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 17 May 2011, 10:00-11:00

Imperial-Penn Group Meeting

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 10 May 2011, 17:00-19:00

Imperial CAS Reading Group

Usernachiket@imperial.ac.uk.

HouseRoom 503/EEE.

ClockWednesday 04 May 2011, 12:30-14:00

Membrane Computing and More

UserDavid Kearney (University of South Australia).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 27 April 2011, 14:00-15:00

Compiling with the Value State Dependence Graph

UserJames Stanier (Sussex).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 27 April 2011, 13:00-14:00

Imperial-Penn Group Meeting

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 12 April 2011, 17:00-18:00

Introduction to face detection methods

UserChuan Cheng (Imperial College London).

HouseRoom 503/EEE.

ClockMonday 04 April 2011, 11:30-12:00

ARC 2011 Conference Debrief

UserNachiket Kapre (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 30 March 2011, 14:00-15:00

Imperial-UPenn Group Meeting on FPGA Variation/Aging

UserSpeaker to be confirmed.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 22 March 2011, 16:00-18:00

Symbolic evaluation of GPU software

UserDavid Huw Jones (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 21 March 2011, 11:30-12:00

Application Specific Memory Access, Reuse and Reordering for SDRAM

UserSamuel Bayliss (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 21 March 2011, 10:00-11:00

FPGA 2011 Debrief

UserNachiket Kapre (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 08 March 2011, 15:00-16:00

No longer available

UserTheo Drane (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 07 March 2011, 13:00-14:00

Optimize massively parallel stochastic difference simulations

UserXiang Tian (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 07 March 2011, 11:30-12:00

Resource-Constrained Object-Based Compression for Surveillance Systems

UserAdam Powell (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 28 February 2011, 11:30-12:00

PPoPP/HPCA Conference Debrief

UserNachiket Kapre (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 22 February 2011, 13:00-14:00

Bio-inspired visual memory: a report on the motivation and methodology

UserJian Xiong Liu (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 21 February 2011, 11:30-12:00

Markov Chain Monte Carlo using reconfigurable hardware

UserGrigoris Mingas (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 14 February 2011, 11:30-12:00

Implementation of a Haar-like feature classifier based on an FPGA

UserChuan Cheng (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 07 February 2011, 11:30-12:00

Probabilistic Computing: A Case Study of Ripple Carry Adders

UserSumanta Chaudhuri (Imperial College).

HouseRoom 503/EEE.

ClockTuesday 01 February 2011, 12:00-12:00

Playing with Polynomials and Precision

UserDavid P Boland (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 12 January 2011, 16:00-17:00

Towards Analytical Methods for FPGA Architecture Investigation

UserSteve Wilton (University of British Columbia).

HouseHuxley Building, 344A.

ClockThursday 04 November 2010, 16:00-17:00

No longer available

UserTheo Drane (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 24 September 2010, 15:00-16:00

POSTPONED

UserSamuel Bayliss (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 09 September 2010, 16:00-17:00

MPC for Deeply Pipelined FPGA Implementation

UserJuan (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 24 August 2010, 15:30-16:30

POSTPONED

UserAbid Rafique (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 22 July 2010, 13:00-14:00

Title to be confirmed

UserDavid P Boland (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 15 July 2010, 16:00-17:00

No longer available

UserTheo Drane (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 24 June 2010, 15:00-16:00

FCCM 2010: Automated Precision Analysis: A Polynomial Algebraic Approach

UserDavid P Boland (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 11 May 2010, 12:00-13:00

Sampling and Controlling Faster than the Computational Delay

UserDominic Buchstaller (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 22 April 2010, 16:00-17:00

TALK POSTPONED

UserDominic Buchstaller (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 22 March 2010, 13:00-14:00

Power consumption modelling of FPGAs

UserAlastair Smith (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 11 March 2010, 16:00-17:00

ARC 2010: Keynote Preview

UserProfessor Peter Cheung (Imperial College London).

HouseRoom 503/EEE.

ClockWednesday 03 March 2010, 14:30-15:00

ARC2010: Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods

UserDavid P Boland (Imperial College).

HouseRoom 503/EEE.

ClockWednesday 03 March 2010, 14:00-14:30

ARC2010: A Fused Hybrid Floating-Point and Fixed-Point Dot-product for FPGAs

UserAntonio Roldao Lopes (PhD at IC).

HouseRoom 503/EEE.

ClockWednesday 03 March 2010, 13:30-14:00

ARC2010: Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA

UserChalermpol Saiprasert (Imperial College).

HouseRoom 503/EEE.

ClockWednesday 03 March 2010, 13:00-13:30

TALK POSTPONED

UserDominic Buchstaller (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 25 February 2010, 16:00-17:00

Degradation in FPGAs: Measurement and Modelling

UserEd Stott, CAS Group.

HouseRoom 908/EEE.

ClockMonday 15 February 2010, 14:00-15:00

A Hybrid Floating-point and Fixed-point Dot-product Design for FPGAs

UserAntonio Roldao Lopes (PhD at IC).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 08 February 2010, 15:00-16:00

Hardware design of MPC controllers

UserJuan (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 25 January 2010, 15:00-16:00

No longer available

UserTheo Drane (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 10 December 2009, 13:00-14:00

Mini FPT: "Modelling degradation in FPGA lookup tables"

UserEdward A Stott (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 01 December 2009, 13:30-13:45

Title to be confirmed

UserSamuel Bayliss (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 26 November 2009, 13:00-14:00

The Role of Computer-Assisted Numerical Proofs in Efficient Hardware Design

UserGeorge A Constantinides (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 12 November 2009, 13:00-14:00

CANCELLED

UserNone.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 12 November 2009, 12:00-13:00

Self-Hosted Placement for Massively Parallel Processor Arrays

UserGuy Lemieux, University of British Columbia, Vancouver, Canada.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 29 October 2009, 15:00-16:00

FPGA Architecture Optimisation Using Geometric Programming

UserAlastair Smith (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 21 October 2009, 14:00-15:00

Robust Stability and Performance for Multiple Model Switched Adaptive Control

UserDominic Buchstaller (Imperial College).

HouseDenis Gabor Seminar Room, 611.

ClockWednesday 21 October 2009, 13:00-14:00

Accelerating the dot-product operation using Field Programmable Gate Arrays

UserAntonio Roldao Lopes (PhD at IC).

HouseRoom 611, EEE.

ClockThursday 01 October 2009, 12:00-13:00

Area Estimation and Optimisation of FPGA Routing Fabrics

UserAlastair Smith (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 19 August 2009, 09:00-10:00

System Design – Leveraging Capability, Overcoming Complexity

UserSuhaib Fahmy (Imperial College London).

HouseRoom 611, EEE.

ClockThursday 06 August 2009, 13:00-14:00

Heterogeneous architecture exploration using analytical tools and VPR 5.0

UserAsma Kahoul (Imperial College).

HouseRoom 611, EEE.

ClockThursday 23 July 2009, 12:00-13:00

Predicting Bounds on Ranges of Variables in an Algorithm using Polynomials

UserDavid P Boland (Imperial College).

HouseRoom 611, EEE.

ClockFriday 10 July 2009, 12:00-13:00

TIADC Mismatch Compensation

UserProf Lim Yong Ching (Nanyang Technological University, Singapore) .

HouseRoom 611, EEE.

ClockThursday 14 May 2009, 11:00-12:00

Parallel Computation of the Phylogenetic Likelihood Kernel in HW and SW

UserDr. Alexandros Stamatakis, Exelixis Lab, Department of Computer Science, Technische Universitat Munchen.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 31 March 2009, 14:30-15:30

Static scheduling of SDRAM commands using constraint logic programming

UserSam Bayliss (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 25 March 2009, 12:00-13:00

ARC: Practice Talk 2

UserAsma Kahoul (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 12 March 2009, 12:00-13:00

ARC Preview: Heterogeneous Architecture Exploration: Analysis vs Parameter Sweep

UserAsma Kahoul (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 05 March 2009, 15:00-15:30

Challenges in FPGA Research

UserDr Peter Jamieson (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 26 February 2009, 12:00-13:00

Multiplication Without Multipliers: Algorithms, Applications, and Extensions

UserDr Oscar Gustafsson (Linkoping University).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 20 February 2009, 12:00-12:45

Challenges in FPGA Research

UserDr Peter Jamieson (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 19 February 2009, 12:30-13:00

Predicting minimal error bounds through an algorithm

UserDavid Boland ( Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 19 February 2009, 12:00-12:30

Fixed-Point Arithmetic in DSP

UserDr George A Constantinides (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 22 January 2009, 16:00-17:00

FPGA architecture optimisation using geometric programming

UserAlastair Smith (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 22 January 2009, 12:00-13:00

Transforming image processing algorithms for efficient FPGA implementation

UserDonald Bailey, Massey University, New Zealand.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 21 January 2009, 11:00-12:00

FPT Report-Back

UserAntonio Roldao (PhD@IC).

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockWednesday 17 December 2008, 15:00-15:30

Best Papers of Autumn Term

UserSeveral.

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockWednesday 17 December 2008, 14:00-15:00

'A linear algebra framework for automatic determination of optimal data layouts' by Mahmut Kandemir et al.

UserSam Bayliss (Imperial College London).

HouseRoom 503/EEE.

ClockWednesday 17 December 2008, 12:00-12:30

Heterogeneous Architecture Exploration: Analysis vs. Parameter sweep

UserAsma Kahoul (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 01 December 2008, 12:00-13:00

(FPT Preview) Optimizing Coarse-Grained Units in Floating Point Hybrid FPGAs

UserChi Wai Yu, Department of Computing, Imperial College London.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 28 November 2008, 16:00-16:30

(FPT Preview) Modelling and Compensating for Clock Skew Variability in FPGAs

UserDr Pete Sedcole (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 28 November 2008, 15:30-16:00

(FPT Preview) A Scalable FPGA Architecture for Non-linear SVM Training

UserMarkos Papadonikolakis (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 28 November 2008, 12:00-13:00

(FPT Preview) Co-optimisation of Datapath and Memory in Outer Loop Pipelining

UserKieron Turkington (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockFriday 28 November 2008, 11:00-12:00

CG: Optimizing FPGA Speed using Custom Precision

UserAntonio Roldao (PhD@IC).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 19 November 2008, 14:00-15:00

Improving Real-time Observability in Embedded Logic Analysis

UserNicola Nicolici (McMaster University, Canada).

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockFriday 07 November 2008, 16:00-17:00

COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip

UserProf Nikil Dutt (University of California, Irvine).

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockFriday 07 November 2008, 11:30-12:30

On Logical Masking Effects of Soft Errors

UserProf. Sudhakar M. Reddy (University Of Iowa, USA).

HouseDennis Gabor Seminar Room (611), EEE Department.

ClockFriday 07 November 2008, 10:30-11:30

A New Approach for Exploring Numerical Accuracy

UserDavid Boland ( Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 03 November 2008, 12:00-13:00

Wirelength Modeling for Homogeneous and Heterogeneous FPGA Architectural Development

UserAlastair Smith (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 20 October 2008, 12:00-13:00

Accelerating Iterative Methods Using FPGAs

UserAntonio Roldao (PhD@IC).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 07 October 2008, 14:00-15:00

Developing analytical techniques for FPGA architecture design

UserAlastair Smith (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 06 October 2008, 11:00-12:00

Some Ideas from my Sabbatical

UserDr George A Constantinides (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 24 September 2008, 10:00-11:00

Fault Tolerance and Reliability in FPGAs

UserEdward Stott (Imperial College).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockWednesday 20 August 2008, 14:00-15:00

Memory and Datapath optimisation for FPGA co-processors

UserKieron Turkington (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 14 August 2008, 14:00-15:00

Four Important Concepts to Consider when Using Multicore Clusters

UserDr George A Constantinides (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockMonday 11 August 2008, 11:30-12:30

An FPGA-based Implementation of the MINRES Algorithm

UserDavid Boland, Imperial College London.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 05 August 2008, 11:30-12:15

Report from RSSI

UserDavid Boland ( Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 15 July 2008, 15:00-15:30

Low-Power Design for Reconfigurable Computing

UserDr George A Constantinides (Imperial College London).

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockTuesday 15 July 2008, 11:30-12:30

Investigating I/O and Memory Bandwidth trade-offs for Iterative Algorithms

UserDavid Boland, Imperial College London.

HouseLevel 9 Mahanakorn Lab., EE Dept..

ClockThursday 03 July 2008, 12:00-13:00

From the Horse's Mouth - Architecture of Stratix III

UserVaughn Betz, Altera Corp.

HouseRoom 611, EEE.

ClockTuesday 01 July 2008, 11:00-12:00

If you have a question about this list, please contact: George A Constantinides; Wiesia R Hsissen; David Winstanley; James Davis; John Wickerson. If you have a question about a specific talk, click on that talk to find its organiser.

 

Changes to Talks@imperial | Privacy and Publicity