Imperial College London > Talks@ee.imperial > CAS Talks > Discussion on FPGA implementation of decision tree predicting process in the context of incremental decision tree induction

Discussion on FPGA implementation of decision tree predicting process in the context of incremental decision tree induction

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If you have a question about this talk, please contact Grigorios Mingas.

In this talk, I’d like to discuss about the limitation existing in the state of art hardware design of decision tree predicting (classification) process in FPGA when I try to incorporate it into an FPGA based incremental decision tree training architecture. In addition, I’d like to introduce an alternative design that is optimised for high speed predicting and can fulfil the requirement by the training architecture.

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