Imperial College London > Talks@ee.imperial > CAS Talks > The Many Lives of an FPGA DSP Block

The Many Lives of an FPGA DSP Block

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A recent trend has seen FPG As gain a variety of hard blocks. These offer improved performance and energy for regularly used operations. DSP blocks were added to FPG As, over the last few generations of devices, to help accelerate filters and other multiply-accumulate type operations. In the most recent devices from Xilinx, the DSP48E1 primitive is highly configurable, on a cycle-by-cycle basis, and can perform a wide variety of operations. This talk will present the iDEA soft processor built around a DSP block, as well as discuss other novel ways to exploit such resources. Work on efficient mapping of arithmetic to DSP blocks will also be discussed. Finally, other projects underway at NTU in the general area of reconfigurable computing will be briefly presented, including work on automating partial reconfiguration.

Bio: Suhaib A Fahmy received the M.Eng. degree in information systems engineering and the Ph.D. degree in electrical and electronic engineering from Imperial College London, UK, in 2003 and 2007, respectively. From 2007 to 2009, he was a Research Fellow with the University of Dublin, Trinity College, and a Visiting Research Engineer with Xilinx Research Labs, Dublin. Since 2009, he has been an Assistant Professor with the School of Computer Engineering, Nanyang Technological University, Singapore. His research interests include reconfigurable computing, high-level system design, and computational acceleration of complex algorithms. Dr Fahmy was a recipient of the Best Paper Award at the IEEE Conference on Field Programmable Technology in 2012, the IBM Faculty Award in 2013, and is a senior member of the ACM and IEEE .

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