Program Slicing for High-level synthesis

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• Shane Fleming (Imperial College)
• Monday 15 May 2017, 15:00-16:00
• Level 9 Seminar Room, EE Dept..

If you have a question about this talk, please contact George A Constantinides.

In this talk, I present a technique used to construct software compiler optimisations called program slicing and I demonstrate how effectively it applies to high-level synthesis (HLS) tools. A program slicer accepts as inputs, a program P, and a subset of the behaviour of P. It outputs a minimal version of P that produces that behaviour. For software compilers, one application of program slicing is to construct “helper threads”. These threads concurrently execute with the main thread to precompute runtime events. For instance, they can run ahead to prefetch data or set branch predictors, resulting in an overall speedup for the main thread. While this approach does improve software performance, it often suffers from the communication latency required to transfer information between the helper and main threads. However, for HLS this is not the case, as a custom architecture is constructed from the input, enabling custom communication channels to connect the main and helper threads.

This talk will discuss a program slicing API that we have developed for the LegUp HLS tool, called SliceUp. Using SliceUp, a developer can construct optimisations that automatically generate “helper circuits” for the input description. To demonstrate this, I will explore two novel case studies in detail: the first generating helper circuits to replicate only a subset of behaviour for selective soft-error coverage, and the second generating helper circuits to precompute load operations to hide memory latency in irregular applications. Finally, I will discuss some future possibilities and application areas that could make use of SliceUp.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EE Dept.

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