The VENICE Soft Vector Processor

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• Guy Lemieux (UBC)
• Monday 14 November 2011, 11:00-12:00
• Level 9 Mahanakorn Lab., EE Dept..

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Vector processing is an effective way to speed up data-parallel workloads that can be implemented very compactly and efficiently in an FPGA . The VENICE soft vector processor is optimized to work with the Nios II soft processor, particularly for small vector widths. On a suite of benchmarks, VENICE achieves 5.0x higher performance-per-ALM than Nios II alone, which is 1.7x higher than the previous-best soft vector processor, VEGAS . Architectural changes that help make VENICE smaller than VEGAS , such as eliminating the vector address register file, also help make VENICE easier to program. This talk will cover the impact of the architectural changes in terms of performance, area, and ease of use.

Bio:

Guy Lemieux is an Associate Professor at the University of British Columbia. His research interests are focused around FPGA architecture and CAD . Most recently, he has been advocating the use of vector processors in FPG As to accelerate data-parallel workloads, and the use of time-multiplexed, coarse-grained ALUs in FPG As to greatly accelerate place&route runtimes. In a former lifetime, he was a graduate student at the University of Toronto where he was responsible for Stratix-like FPGA interconnect research during his PhD thesis, the design and construction of NUM Achine, a 64-way cache-coherent shared-memory multiprocessor, for his MASc thesis, and the first “timing-driven” academic FPGA router that handled long wire segments, SEGA , for his BASc thesis.

This talk is part of the CAS Talks series.

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