Imperial College London > Talks@ee.imperial > CAS Talks > Area-efficient Division for ARbitrary-precision Constant-Hardware ITErative CompuTe

Area-efficient Division for ARbitrary-precision Constant-Hardware ITErative CompuTe

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Many iterative algorithms contain a set of operations including division, multiplication and addition. Traditionally, carry direction reversal between most-significant-digit-first (MSDF) division and least-significant-digit-first (LSDF) addition or multiplication stalls computation until all digits in the preceding operation have been calculated. Numerical operations are also normally implemented using finite-precision datatypes, so precision must be chosen prior to the iterative algorithm’s commencement. Subsequently, users typically over-budget their precision in order to achieve a convergent result. To address these issues, we propose an area-efficient architecture for ARCHITECT (ARbitrary-precision Constant-Hardware ITErative CompuTe) division and composite division/multiplication-addition arithmetic on field-programmable gate arrays (FPGAs), which is able to complete.

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