Bit-Level Manipulated Graph Neural Networks

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• Pedro Gimenes (Imperial College)
• Monday 04 December 2023, 13:00-14:00
• Department of Electrical and Electronic Engineering, Room 909B.

If you have a question about this talk, please contact George A Constantinides.

In recent times, Graph Neural Networks (GNNs) have attracted great attention due to their classification performance on non-Euclidean data. FPGA acceleration proves particularly beneficial for GNNs given their irregular memory access patterns, resulting from the sparse structure of graphs.

These unique compute requirements have been addressed by several FPGA and ASIC accelerators, such as HyGCN and GenGNN. Despite the relative success of hardware approaches to accelerate GNN inference on FPGA devices, previous works have shown to be limited to small graphs with up to 20k nodes, such as Cora, Citeseer and Pubmed. Since the computational overhead of GNN inference grows with increasing graph size, current accelerators are not well-prepared to handle medium to large-scale graphs, particularly in real-time applications.

This work introduces AGILE (Accelerated Graph Inference Logic Engine), an FPGA accelerator aimed at enabling real-time GNN inference for large graphs by exploring a range of hardware optimisations. A new asynchronous programming model is formulated, which reduces pipeline gaps by addressing the non-uniform distribution in node degrees. Inspired by GNN quantisation analysis from Taylor et al., a multi-precision node dataflow is proposed, improving throughput and device resource usage. Finally, an on-chip Prefetcher unit was implemented to cut down memory access latency. Evaluation on Planetoid graphs shows up to 2.8x speed-up against GPU counterparts.

This talk is part of the CAS Talks series.

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