MLIR - Connecting domain-specific languages to domain-optimized accelerators

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• Samuel Bayliss (AMD)
• Wednesday 05 July 2023, 16:00-17:00
• Department of Electrical and Electronic Engineering, Room 503.

If you have a question about this talk, please contact George A Constantinides.

Hardware specialization is a recognized route to compute efficiency, and has had particular recent success through a “Cambrian Explosion” of new commercialized hardware architectures designed to efficiently execute AI workloads.

This brings with it a need to express diverse low-level hardware capabilities within compiler frameworks. MLIR ( Multi-level Intermediate Representation) provides an extensible framework for doing this. In this talk, we describe how MLIR solves a problem in building compilers for domain-specific accelerators and demonstrate how, with it, we’ve built open-source MLIR -AIE and MLIR -AIR dialects to expose the hardware capabilities of AMDs AIE architecture and abstract the important characteristics of a broader class of accelerators for spatial computing.

Samuel Bayliss is a Fellow in the AMD Research and Advanced Development group in San Jose, CA working on Compilers, Runtime and Machine Learning Architectures.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Department of Electrical and Electronic Engineering, Room 503

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