Less is more: graph partitioning for approximate circuit design

Add to your list(s) Download to your calendar using vCal

• Ilaria Scarabottolo (USI Lugano)
• Monday 11 March 2019, 16:00-17:00
• Level 9 Seminar Room, EEE Dept..

If you have a question about this talk, please contact George A Constantinides.

s Approximate Computing is gaining popularity in the academic and industrial community, several techniques have been developed to apply approximation at hardware level. Many of these techniques benefit from an accurate error-model of the circuit to be approximated, and this can be achieved through a novel partitioning approach, applied to the graph representing the circuit. By operating at sub-circuit level, and by exploiting the graph topology, it is possible to determine an accurate estimation of the error that each single component (which could be a gate or a larger unit) can induce on the final circuit output, if that component is removed. This approach allows to trade accuracy for performance, while controlling the maximum error level.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EEE Dept.

Note that ex-directory lists are not shown.