Imperial College London > Talks@ee.imperial > CAS Talks > Injecting many FPGA configuration faults

Injecting many FPGA configuration faults

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If you have a question about this talk, please contact George A Constantinides.

FPGA fault injection is used to test an FPGA circuit’s robustness to bitflips in the device configuration memory. The gold standard for this class of testing is in-hardware fault injection where: a real FPGA device is configured with a circuit, a target configuration bit is flipped, the output response is recorded, and the device is recovered to the original configuration. However, flipping bits occasionally results in the device entering a highly unstable state, where recovery can take a long time. These long recovery times make this form of testing a slow process that scales poorly with the size of the circuit. In this talk I will present an automated, scalable, and reliable testing rig that uses multiple Xilinx Zynq FPGA devices in parallel. Using our rig we have exhaustively explored single bitflip faults in the configuration memory of multiple circuits, enabling us to identify statically predictable bits guaranteed to cause system lock-up. We have also been able to use our rig to test the Xilinx Essential Bits tool, a tool that tells the circuit designer the subset of configuration bits potentially critical to circuit operation, and have results that indicate that there may be configuration bits which when flipped cause an erroneous output that Essential Bits fails to capture.

This talk is part of the CAS Talks series.

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