Streaming Abstractions for FPGA High Level Synthesis

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• John McAllister (Queen's University Belfast)
• Monday 03 July 2017, 14:00-15:00
• Level 9 Seminar Room, EE Dept..

If you have a question about this talk, please contact George A Constantinides.

High level synthesis tools for FPGA are becoming increasingly powerful and do an effective job of translating kernels, or functions, into custom circuit accelerators. There are, however, open questions regarding the efficiency, in terms of performance per unit cost of the resulting accelerators, both standalone or in the context of practical FPGA computing platforms. This reduction in efficiency is typically accepted as a necessary evil whenever the design entry point for any embedded technology moves to a higher level of abstraction. This presentation asks, however, whether this need necessarily be the case for FPGA . Current HLS tools are designed to offer general-purpose synthesis capability, but what if this where not the case? What if it were able to harness domain-specific features? Could different intermediate representations, compilation techniques or processing architectures be harnessed, with the objective of producing more efficient results? This talk explores and presents results of this vision in the context of streaming workloads.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EE Dept.

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