Compiling with the Value State Dependence Graph

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• James Stanier (Sussex)
• Wednesday 27 April 2011, 13:00-14:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact George A Constantinides.

The Value State Dependence Graph (VSDG) is a compiler intermediate representation that represents programs by data flow, maintaining only the essential control flow needed. This makes program optimisations really efficient, neat and easy to write. However, generating code from the VSDG has been difficult, as we must restore the order of instructions we’ve stripped away. Previous attempts have been naive or NP-Complete. We show how we translate the VSDG into a parallel program, and then schedule the parallel program to execute on a single processor.

Why might you like this talk? - The VSDG looks quite like an abstraction of hardware. - We think that generating an FPGA from a VSDG could be really interesting! Future work? - If you’ve been working at the hardware level for a long time, come and see what goes on inside the guts of a compiler. How can compiler writers help you do your job better?”

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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