ZepAlloc: Three-Stage Hardware Dynamic Memory Manager in FPGA

Add to your list(s) Download to your calendar using vCal

• Hilda Xue (CAS)
• Monday 11 December 2017, 15:00-16:00
• Level 9 Seminar Room, EE Dept..

If you have a question about this talk, please contact George A Constantinides.

Memory management is well researched for software to gain memory efficiency and allow design and implementation abstractions. As the chip-density increases, larger and more memory-footprint complex applications are now allowed to be realised in FPG As. However, implementing them require huge effort with the conventional static memory usage. In addition, current HLS tools do not support memory management functions such as C malloc() and free(). In our prior work, SysAlloc, we have demonstrated the feasibility of using a hardware memory manager to provide malloc()-free() functionalities to both software and hardware clients on the same bus managing DDR -scale range of memory, however, the latency cannot be bounded. Now we propose a new hardware memory manager, ZepAlloc, that aims to provide malloc()-free() with close-to-transparent latency. ZepAlloc architecture contains three stages: Queueing, Paging and list-based Buddy System. In this talk I will give an overview of the problems we are solving and show the design and part of our experimental results.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EE Dept.

Note that ex-directory lists are not shown.