Low Overhead Mitigation of Radiation Effects in SRAM-Based FPGAs for Avionics

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• Michail Vavouras (Imperial College London)
• Monday 15 June 2015, 11:30-12:30
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact Grigorios Mingas.

In this talk, the problem of a radiation particle striking an SRAM FPGA in an aircraft and causing a bit flip in its configuration memory will be introduced. The effect of the bit flip (Single Event Upset or SEU ) could be catastrophic for the user application leading to a system failure or might not affect the function of the system depending if this bit is used by the application at the occurrence of the fault (critical bit). Traditional mitigation techniques leverage different schemes of modular redundancy and configuration memory scrubbing for fault detection and fault repair respectively. However, dual modular redundancy (DMR) leads to significant area and power overheads compared to the baseline application. Moreover, CRC -Based or ECC -Based triggered scrubbing may lead to unnecessary scrub cycles while blind scrubbing may lead to transistor ageing and energy overheads. A novel, DMR technique using the partial reconfiguration feature of SRAM FPG As coupled with an error-triggered scrubbing strategy is proposed. This technique saves area at the cost of lower fault coverage compared to the full DMR .

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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