Imperial College London > Talks@ee.imperial > CAS Talks > Project Trellis: enabling open source tools for the Lattice ECP5 FPGA

Project Trellis: enabling open source tools for the Lattice ECP5 FPGA

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If you have a question about this talk, please contact George A Constantinides.

Project Trellis documents the bitstream and low-level architecture of Lattice ECP5 FPG As, which combined with the Yosys and nextpnr tools enables a full open source flow from Verilog source to a bitstream. These FPG As contain up to 85k logic cells and a range of features including DSPs, multi-gigabit transceivers and advanced IO functionality; unlocking applications such as networking, software-defined radio, high-resolution video, and testing processors powerful enough to run Linux!

The documentation includes core features including logic, RAM and IO tiles. Work continues on both more advanced features and developing a feature-complete open toolchain for the ECP5 .

This presentation will discuss what approach was taken and what tools had been developed to create useful bitstream documentation within the constraints of publicly available interfaces; and then on how the ECP5 architecture was added to the existing open source tools Yosys (synthesis) and nextpnr (place and route).

There will also be a live hardware demonstration of the Yosys, nextpnr and Trellis open source end-to-end flow for the ECP5 .

This talk is part of the CAS Talks series.

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