Addressing DRAM Power Consumption in CNN Accelerators

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• Alexander Montgomerie-Corcoran (Imperial College)
• Monday 15 March 2021, 16:00-17:00
• Teams (in the "CAS Seminars" team).

If you have a question about this talk, please contact George A Constantinides.

The power consumption of the memory subsystem dominates in most CNN accelerators due to the high energy cost of transferring data to and from DRAM as well as the limited on-chip memory size. One method to address this is employing compression schemes to reduce the amount of data transferred, as well as activity coding schemes which reduce dynamic power along the bus. In this talk, the DRAM power consumption for accelerators will be evaluated, and different coding and compression schemes will be discussed.

This talk is part of the CAS Talks series.

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• Andrea Picciau's list
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• Circuits and Systems Group: Internal Seminars
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