Imperial College London > Talks@ee.imperial > CAS Talks > FCCM Practice: Concurrency-Aware Thread Scheduling for High-Level Synthesis
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FCCM Practice: Concurrency-Aware Thread Scheduling for High-Level SynthesisAdd to your list(s) Download to your calendar using vCal
If you have a question about this talk, please contact George A Constantinides. When mapping C programs to reconfigurable hardware, HLS tools seek to reorder instructions so they can be packed into as few clock cycles as the FPGA resources allow. However, when synthesising multi-threaded C, instruction reordering is inhibited by the presence of atomic operations (‘atomics’), such as compare-and-swap. Atomics, the fundamental concurrency primitive in C, are the basis for more abstract concurrency mechanisms such as locks, and for efficient lockfree data structures. Whether a particular atomic can be legally reordered within a thread can depend on the memory access patterns of other threads. Existing HLS tools that support atomics typically schedule each thread independently, and so must be conservative when optimising around atomics. Yet HLS tools are distinguished from conventional compilers by having the entire program available. Can this information be exploited to allow more reorderings within each thread, and hence to obtain more efficient schedules? In this work, we propose a whole-program analysis that determines, for each thread, which pairs of instructions must not be reordered. Our analysis is sensitive to the C11 consistency mode of the atomics involved (e.g. relaxed, release, acquire, and sequentially-consistent). We have used the Alloy model checker to validate our analysis against the C language standard, and have implemented it in the LegUp HLS tool. An evaluation on several lock-free data structure benchmarks indicates that our analysis leads to a 1.6x average whole-program speedup. This talk is part of the CAS Talks series. This talk is included in these lists:
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