The impact of resonant, distributed, frequency and transmission properties of interconnects upon nano-scale VLSI devices reliability and functionality

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• Pavel Livshits
• Monday 22 March 2010, 14:00-15:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact Alastair Smith.

Rapid development of Systems-on-a-Chip (SoC) over the last decade has set tougher signal integrity requirements for on-die signal and power distribution networks. At the same time, only a very few experimental works have been conducted to study the properties of on-die interconnects constituting these networks.

In this talk, results obtained within the framework of our experimental study on global interconnects, constructed as transmission lines, that carry out on-die global signaling and on interconnects constituting power supply and ground grids, are presented. In the study we employed VLSI engineering samples typical for 90 nm and 45 nm CMOS technology nodes.

We found that local voltage fluctuations in power supply and ground grids, excited by on-die logic cell switching have a resonant-like form. This finding resolves the discussed in literature controversy over the need for considering parasitic inductance i.e., the on-die power grids should be described as an RLC circuit.

We experimentally observed and confirmed by modeling that the active element (i.e., CMOS logic cell) influences the frequency properties of power supply and ground grids during its switching (as opposed to before or after switching). Thus, it was shown that frequency properties of both grids are inter-related via the interconnecting active elements.

In our experimental study was found that the impedance matching between CMOS driver and a driven transmission line, and the Ohmic losses of on-die transmission lines, implemented by standard metal layers of modern technology nodes, play an important role in circuits’ performance. The study suggests that impedance mismatch results in excessive power consumption and signal integrity problems. The high Ohmic losses result in a significant distortion and Inter-Symbol Interference of already a few hundreds Mega-Hertz signals.

Our study reveals that relatively low but repetitive voltage oscillations on on-die power supply and ground grids, excited by logic cells switching, may lead not only to logic faults, as it has been regarded, but also to an accumulated damage of VLSI MOSFE Ts. Thus, according to Berkley Reliability Tools models simulations they accelerate the device degradation due to three main wearout mechanisms, such as Time-Dependent Dielectric Breakdown, Negative Bias Temperature Instability and Hot Carrier Injection. The similar device damage, as the study shows, is caused by the impedance mismatch induced distortions of signals supplied to input of on-die CMOS logic cells.

Speaker Bio: Pavel Livshits received the M.Sc degree (Magna Cum Laude) in Electrical Engineering from the Tel-Aviv University in 2006. He is working on his PhD with Bar-Ilan University and Freescale Semiconductor. The field of his research is concern with distributed properties of interconnection lines in nano scale VLSI devices. Within the framework of his graduate research he has co-authored, as a leading author, in three journal papers and six conference proceedings. He has given two invited talks in Albert Ludwig University in Freiburg and Tel-Aviv University. He has been awarded the Faculty Scholarship for Excellence (2005), Doctoral Fellowship of Excellence (2006) and Dean’s Prize for Excellence (2009). He has been working as a main lecturer on a number of courses at his University. He was a member of the organisation committee of the conference in Nanophotonics and Bioengineering (September 2009, Jerusalem).

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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