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Power consumption modelling of FPGAs

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If you have a question about this talk, please contact George A Constantinides.

FPGA modelling has received attention from the architecture design community over the past three years. The advantage of such techniques is the ability to explore design spaces without the need for time-consuming empirical measurements: synthesis, place and route require significant compute power. The last of the traditional device performance metrics to be addressed by modelling, power consumption, is the subject of our latest forray into modelling techniques. This talk will discuss preliminary work on this topic, involving modelling of the power consumed by the routing fabric.

This talk is part of the CAS Talks series.

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