Imperial-Penn Group Meeting

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• Speaker to be confirmed
• Tuesday 24 May 2011, 16:00-18:00
• Level 9 Mahanakorn Lab., EE Dept..

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Speaker: Edward Stott postdoc

Title: Improving FPGA reliability using wear-levelling

Abstract: As VLSI circuits achieve smaller and smaller geometries, reliability is becoming an increasing problem. The flexibility of FPG As enables novel techniques for meeting this challenge, and one such technique is wear-levelling: periodic reconfiguration to eliminate electrical stress hotspots. In this work we have have carried out accelerated-life experiments in FPG As to assess the feasibility of three wear-levelling techniques for reducing timing degradation. All three techniques resulted in significant improvements over a static configuration, and we have demonstrated that wear-levelling is a promising tool for improving FPGA reliability

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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