Imperial College London > Talks@ee.imperial > CAS Talks > SysAlloc2: Three-Stage Memory Allocator for Heterogeneous Systems

SysAlloc2: Three-Stage Memory Allocator for Heterogeneous Systems

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If you have a question about this talk, please contact George A Constantinides.

Bringing dynamic memory usage to heterogeneous system is one way of allowing faster algorithm to synthesis development while achieving higher memory efficiency. In the previous version of SysAlloc, which is a FPGA IP that provides the functionalities of malloc()-free() to all heterogeneous processors (ARM processor, Soft-CPU Nios II/MicroBlaze, FPGA I Ps). Usually when design migrates from static memory usage to dynamic memory usage, the design is slowed due to the memory management tasks that’s hidden from the users. In our case, due to the unbounded number of high latency DDR accesses used in (de-)allocation processes, the allocator is not fast enough to support real-time applications. My current project targets to create SysAlloc2, a fast allocator which aims to minimise the (de-)allocation latency to clients to a close-to-ideal level. The novel 3-stage allocation algorithm is created to hide the latency to client, while a very hardware-friendly communication protocol – size-mapped-register set is used to reduce the latency seen by the clients to close-to-one memory mapped register access latency.

In this presentation, we review the basic concept of memory management design and what is learnt during the process of developing both version of heterogeneous system memory allocators.

This talk is part of the CAS Talks series.

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