Optimize massively parallel stochastic difference simulations

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• Xiang Tian (Imperial College London)
• Monday 07 March 2011, 11:30-12:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact Grigorios Mingas.

As Field Programmable Gate Arrays (FPGAs) get faster and denser, the scope of their applications is getting wider. High performance computing applications, for instance, are an example of such application expansion driven by FPG As’ increasing computational power coupled with their relatively low power consumption compared to state-of-the-art microprocessor technology. However, the floating point operations are still very expensive when implementing on FPG As. To achieve a higher throughput, we can implement computing units with customized word length. The precision issue is then under investigation to ensure the accuracy can meet the requirement. In this work, we are going to present a method to dynamically reconfigure the basic computing elements. Hence, a reconfigurable computing framework and metrics to evaluate the accuracy in real time are to be developed.

This talk is part of the CAS Talks series.

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• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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