On the Nature of Manual RTL Optimisations

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• Theo Drane (Intel)
• Monday 22 February 2021, 16:00-17:00
• Teams.

If you have a question about this talk, please contact George A Constantinides.

Those involved in the industrial design of high performance arithmetic hardware lovingly craft bespoke circuits; a dark art buried in trade secrets, patents and papers.

What is the underlying nature of their optimisations? They represent the last stand against HLS . Can and should these roles vanish? Where should the human / machine line be drawn?

This talk will provide insight into various approaches designers use in RTL optimization with a view to generalisation and automation.

Dr. Theo Drane started working for the Datapath consultancy, Arithmatica, in 2002 after a Mathematics degree from the University of Cambridge, UK. He moved to Imagination Technologies in 2005, where he subsequently founded their Datapath team while studying for a PhD in Lossy Polynomial Datapath Synthesis under Prof. George Constantinides at Imperial College London’s EE Department. In December 2019, after a stint within Cadence Design System’s Logic Synthesis division, Genus, he joined Intel’s Visual Technologies Team. There, he is forming an applied research Numerics group which focuses on all aspects of architecting, implementing, optimizing and formally verifying math intensive hardware.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Teams

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