Imperial College London > Talks@ee.imperial > CAS Talks > The Case for Embedded NoCs on FPGAs

The Case for Embedded NoCs on FPGAs

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If you have a question about this talk, please contact George A Constantinides.

FPGA interconnect is currently low-level, single-bit routing that is configured out of pre-fabricated multiplexers and wires. Connecting ever-larger systems with this low-level interconnect requires a great deal of both design and compile time; consequently, we seek to raise the abstraction level of communication by using packet-switched Networks-on-Chip (NoCs) for some communication paths. We explore the cost and benefit of such networks when they are implemented both in hard (ASIC gates) and soft logic.

By comparing NoC components on FPG As and ASI Cs we quantify the efficiency gap between the two platforms and use the results to understand the design tradeoffs in each space. For a soft NoC router, these results indicate that wide datapaths, deep buffers and a small number of ports and virtual channels (VC) are favorable for FPGA implementation. If one hardens a state-of-the-art VC router instead of modifying the router to suit the FPGA soft fabric, however, the gains are compelling. We show that such a hard router can be integrated with the soft FPGA interconnect with minimal disruption to the overall fabric, while reducing the NoC area by 22X. This hardened NoC reduces both the area and power required for communication vs. that required by the multiplexer-based hierarchical buses configured from the FPGA fabric that are the dominant system-level interconnect on FPG As today.

Time permitting, Dr. Bet will also give a brief overview of other research projects underway in his group.

Speaker Bio:

Dr. Betz has been active in both academic and commercial FPGA research for 20 years, and is currently an Associate Professor at the University of Toronto. The VPR toolset and methodology he developed in his Ph.D. have become the standard for FPGA architecture research and the comparison point for CAD optimization quality, and have been used by over 180 companies and 1100 universities. He co-founded Right Track CAD to commercialize this research; after Right Track’s aquisition by Altera, he spent 11 years at Altera, ultimately as Senior Director of Software Engineering. He is the architect of many features within Altera’s Quartus II CAD system, including the placement and routing engine and the power optimization tools. He is also one of the architects of the Stratix and Cyclone FPGA families. He holds 75 US patents, and six of his publications are included in the “FPGA20” most influential FPGA Symposium papers.

This talk is part of the CAS Talks series.

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