Imperial College London > Talks@ee.imperial > CAS Talks > Self-Hosted Placement for Massively Parallel Processor Arrays

Self-Hosted Placement for Massively Parallel Processor Arrays

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We consider the placement problem as part of the CAD flow for a massively parallel processor arrays (MPPAs). In contrast to traditional placers, which operate on a workstation with only a handful of processor cores, we investigate running the placer on the target architecture itself. As the number of processor elements (PEs) in such a device scales, so too does the computational power available to the placer. This natural scaling helps avoid the long runtimes that afflict FPGA flows.

On a hypothetical 32 × 32 = 1024-core MPPA , the proposed algorithm furnishes placements within 5% of the best-found placement quality with traditional sequential simulated annealing. To do so, the distributed placer requires each PE to consider 1/256th as many swaps as the traditional placer, a computational advantage which scales favourably as the number of cores on the MPPA increases.

About the Speaker

Guy Lemieux is an Associate Professor at The University of British Columbia, where he supervises a small group of students working on FPGA architecture and computing on FPG As. Some of his recent contributions include bit-serial wiring to alleviate bit-parallel datapath congestion, a soft vector processor to accelerate embedded data-parallel tasks rather than painstakingly crafting an RTL accelerator, and a new FPGA architecture based upon an array of processors to alleviate CAD runtime and capacity constraints of traditional FPG As. Guy received 3 degrees at the University of Toronto under the supervision of Profs. David Lewis and Stephen Brown.

This talk is part of the CAS Talks series.

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