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Fuzzing VerilogAdd to your list(s) Download to your calendar using vCal
If you have a question about this talk, please contact John Wickerson. All software eventually relies on hardware to function correctly. Hardware correctness is becoming increasingly important due to the growing use of custom accelerators and field-programmable gate arrays (FPGA) to speed up applications on servers. Ensuring the quality of synthesis tools is vital for the reliability of the hardware and, as a consequence, reliable synthesiser testing is essential. This project aims to improve the quality of synthesisers by testing them using randomly generated and correct Verilog, comparing the equivalence of the design with the synthesised logic. The main contribution of this project is a method of generating behavioural and procedural Verilog that does not contain undefined behaviour, which is implemented in a tool called VeriFuzz. In addition, this project proposes a Verilog test-case reducer to locate the bugs that were found. Finally, the bugs that were found in different synthesisers are analysed using qualitative and quantitative results. Every synthesiser that was tested was found to introduce discrepancies between the logic and the design, and some synthesisers crashed when given valid input. VeriFuzz found 21 unique bugs, of which 8 were reported to tool vendors and 3 were fixed. This talk is part of the CAS Talks series. This talk is included in these lists:
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