[FCCM'19 practice talk] LUTNet: Rethinking Inference in FPGA Soft Logic

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• Erwei Wang (Imperial College)
• Monday 15 April 2019, 16:00-17:00
• Level 9 Seminar Room, EEE Dept..

If you have a question about this talk, please contact James Davis.

Research has shown that deep neural networks contain significant redundancy, and that high classification accuracies can be achieved even when weights and activations are quantised down to binary values. Network binarisation on FPG As greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA ’s fundamental building block, the K-LUT, is capable of implementing far more than an XNOR : it can perform any K-input Boolean operation. Inspired by this observation, we propose LUT Net, an end-to-end hardware-software framework for the construction of area-efficient FPGA -based neural network accelerators using the native LUTs as inference operators. We demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarised neural network implementation, we achieve twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EEE Dept.

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