Imperial College London > Talks@ee.imperial > CAS Talks > CG: Optimizing FPGA Speed using Custom Precision

CG: Optimizing FPGA Speed using Custom Precision

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With the continuing exploration of accelerating iterative methods on FPG As, in this upcoming seminar, I will present the latest results obtained from analyzing the speed-up of an FPGA vs a CPU (in double precision) by reducing the word-length. I will also show a plot of the different number of iterations obtained from performing every sum reduction (of the CG method) sequentially or in a tree, for the current MPC Citation Model Aircraft testbench. In addition, I will show and request feedback on a preliminary poster on for the banded implementation paper that is to be presented at FPT ’08.

This talk is part of the CAS Talks series.

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