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CAS Seminar on FPGA Variability, and Architecture (Guest speaker from Japan)

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Delay Variability: A Challenging Opportunity

Presenter: Justin Wong

Abstract: An introduction to the problem of delay variability in FPG As in terms of timing performance/yield, and the challenges we have faced on developing measurement tools to characterise and better understand its effect in real FPG As. Such developments and findings create great opportunities on mitigation strategies that can potentially gain extra timing performance out of FPG As with variation.

Classification of variation maps: An efficient technique to combat process variation in FPG As

Presenter: Zhenyu Guan

Abstract: Technology scaling causes increasing and unavoidable delay variability in FPG As. This paper describes an approach to reduce the delay of the critical path in a design by applying variation aware placement. A full chipwise placement is realized through Versatile Placement and Routing tools (VPR) modification to achieve 4.84% improvement on average. By using variation maps measured from 129 Altera Cyclone III FPG As (DE0 boards), we demonstrate how spatially correlated variation patterns can be divided into clusters and how the cluster-based method can be used to reduce overall run-time in variation-aware placement and routing (P&R) for FPG As while maintaining good timing improvements 2.85% comparable to full chipwise P&R.

Area Evaluation of Memory-based PLD Architecture by Mapping Arithmetic Circuits

Presenter: Dr. Kazuya Tanigawa (Visitor from Hiroshima City University, Japan)

Abstract: In this presentation, I will introduce a Memory-based Programmable Logic Device (MPLD) which goal is to improve the chip area efficiency of conventional reconfigurable device. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas FPGA consists of LUTs (logic elements) and switch blocks (routing elements). MPL Ds contain logic circuits more efficiently than FPG As because of their flexibility and area efficiency. In this presentation, I will show the comparison results of the required chip area for mapping several arithmetic units on MPLD and FPGA .

Dr. Kazuya Tanigawa is a research associate in the Department of Computer Enginnering in Hiroshima City University. His main research interests are developing new reconfigurable architectures, processors and their compilers.

This talk is part of the CAS Talks series.

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