Overclocking Datapath for Latency-Error Tradeoff

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• Kan Shi (Imperial College)
• Thursday 13 September 2012, 13:00-14:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact Grigorios Mingas.

Relaxing constraints of 100% accuracy in datapath can provide the freedom to create designs with better performance or energy efficiency. We develop probabilistic models, which enable us to explore these trade-offs for key arithmetic primitives. We show that because specific input patterns are required to cause timing violations and that these patterns arise rarely, a lower expected error can be attained by allowing some timing variations to occur, instead of reducing the precision of a circuit to meet a target latency. Experiments show that a mean reduction of 5.6X—36.7X in error expectation and an improvement of 7.2dB—19.7dB in signal-to-noise ratio can be obtained for practical applications.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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