TAPA: Fast, High-Frequency, Expressive Dataflow HLS Framework

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• Jason Cong (UCLA)
• Wednesday 27 March 2024, 16:00-17:00
• EEE Room 611.

If you have a question about this talk, please contact George A Constantinides.

TAPA is a task-parallel dataflow high-level synthesis (HLS) framework that (1) improves the final clock frequency by 2X compared to Vivado based on the AutoBridge methodology, and (2) compiles 7X faster than Vitis HLS based on the RapidStream methodology, both employs automated interconnected pipelining, coupled with physical planning driven HLS . TAPA also extends the Vitis HLS syntax for richer expressiveness. TAPA framework won two Best Paper Awards at FPGA ’21 and FPGA ’22, and has been used successfully for developing efficient accelerators for a large number of applications, including stencil computation, graph processing, systolic arrays, and sparse linear algebra. TAPA is being extended to an industry-strength tool by RapidStream Design Automation, a startup by some of TAPA ’s original developers.

Joint work with Licheng Guo, Yuze Chi, Jason Lau, Yun Zhou, Pongstorn Maidee, Chris Lavin, Linghao Song, Weikang Qiao, Jie Wang, Ecenur Ustun , Jianyi Cheng, Alireza Kaviani, Zhiru Zhang.

Speaker Bio:

JASON CONG is the Volgenau Chair for Engineering Excellence Professor at the UCLA Computer Science Department (and a former department chair), with joint appointment from the Electrical and Computer Engineering Department. He is the director of Center for Domain-Specific Computing (CDSC) and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory. Dr. Cong’s research interests include novel architectures and compilation for customizable computing, synthesis of VLSI circuits and systems, and quantum computing. He has over 500 publications in these areas, including 18 best paper awards, and 4 papers in the FPGA and Reconfigurable Computing Hall of Fame. He and his former students co-founded AutoESL, which developed the most widely used high-level synthesis tool for FPG As (renamed to Vivado HLS and Vitis HLS after Xilinx’s acquisition). He is member of the National Academy of Engineering, and a Fellow of ACM , IEEE, and the National Academy of Inventors. He is recipient of the SIA University Research Award, the EDAA Achievement Award, and the IEEE Robert N. Noyce Medal for “fundamental contributions to electronic design automation and FPGA design methods”.

This talk is part of the CAS Talks series.

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