Hardware verification^2. Uncovering bugs in Formal Equivalence Checkers using fuzzing.

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• Michalis Pardalos (Imperial College)
• Monday 16 October 2023, 13:00-14:00
• Department of Electrical and Electronic Engineering, Room 909B.

If you have a question about this talk, please contact George A Constantinides.

Formal equivalence checking (FEC) is a powerful tool in the modern verification engineer’s arsenal. These tools allow comparing software specifications in C/C++ against RTL implementations in Verilog or VHDL and are trusted enough to be used for design sign-off. Bugs in them can, therefore, be very high-impact. We have developed equifuzz: a fuzzer for FECs, which differentially tests SystemC equivalence checkers against a reference implementation and which we have used to uncover bugs in commercial FECs.

This talk is part of the CAS Talks series.

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• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Department of Electrical and Electronic Engineering, Room 909B

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