Tuning Network Topology - existing works, and future directions

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• Aditya Rajagopal
• Monday 24 June 2019, 16:00-17:00
• Level 9 Seminar Room, EEE Dept..

If you have a question about this talk, please contact George A Constantinides.

Convolutional Neural Networks (CNNs) are currently the state-of-the-art technique used in image recognition. Ever since AlexNet managed to outperform humans on the ImageNet dataset in 2012, the use of CNNs in practical applications such as self-driving cars, drones, and phones has rapidly accelerated.The typical pipeline for developing such a CNN is to have experts design the structure and tune the hyperparameters of these networks. Following this, the network is trained on many GPUs housed in large server farms on a given dataset. The choice of dataset used is either something generic such as ImageNet, or a hand crafted dataset specific to the target application at hand. Inference then takes place on the device that the network is deployed on. In most cases these devices lie on the edge and hence have limited hardware capabilities. In order to make inferencing efficient, researchers have classically looked into various approaches such as but not limited to making custom hardware tuned heavily to the compute patterns of CNN inferencing, reducing the precision at which computations are done and pruning networks to reduce both memory and compute requirements. More recently as the compute capability of servers has improved, researchers have begun epxloring the field of Network Architecture Search (NAS) to optimise the architecture of the network for both accuracy and hardware constraints. Such a pipeline means that every time the dataset seen or the hardware deployed changes, the design process of a CNN needs to begin again at some point within this pipeline. The talk will look into existing work in the field of searching for network topologies, what gaps may exist and potential future directions for research in the field that would allow for increased automation and adaptability in this design pipeline.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EEE Dept.

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