A custom hardware architecture for state of the art Semi-dense mapping

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• Konstantinos Boikos (Imperial College)
• Monday 01 October 2018, 16:00-17:00
• Level 9 Seminar Room, EEE Dept..

If you have a question about this talk, please contact George A Constantinides.

In this talk we will discuss a novel, SLAM -specific architecture to perform depth estimation for direct semi-dense SLAM . We designed an architecture with a combination of dataflow processing and local on-chip caching to match the unique demands of these algorithms. Centre-stage take dynamic iteration pipelines, mixed with traditional streaming units for high performance and increased performance per watt when accelerating this type of algorithm. The architecture was implemented on an off-the-shelf Xilinx ZC706 FPGA -SoC and achieved a rate consistently above a target 60 mapped frames per second at a resolution of 640×480, with an estimated power consumption under 5 watts, achieving performance on par to a highly-optimised parallel implementation on a high-end desktop CPU at an order of magnitude better power consumption.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EEE Dept.

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