Efficient Computing In-memory Architectures for FPGA-based Deep Learning Acceleration

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• Yuzong Chen (Cornell Tech)
• Tuesday 26 March 2024, 13:00-14:00
• https://utoronto.zoom.us/j/82613229697.

If you have a question about this talk, please contact George A Constantinides.

Modern FPGA -based deep neural network (DNN) inference mainly relies on the on-chip block random access memory (BRAM) for model storage. However, DNN is typically memory-bound and its energy consumption is dominated by the memory access. In this talk, I will discuss how we can deploy computing in-memory to the existing BRAM architecture on FPG As. The resulting BRAM architecture, called BRAMAC , can compute multiply-accumulate (MAC) operations within BRAM , which significantly reduces the cost of memory access and offers much higher computing throughput than existing FPGA architectures. Unlike many prior computing in-memory works based on application-specific integrated circuits (ASICs), BRAMAC has small area overhead by only performing computation in the digital domain and eliminating expensive analog-digital conversion. Moreover, during BRAMAC computation, other FPGA resources can seamlessly access its data without the need for a separate BRAM buffer. Hence, BRAMAC can simultaneously perform computation and maintain full functionality as a memory unit to truly complement other compute resources on FPG As. Finally, I will show how BRAMAC can be extended to support mixed-precision computation and dataflow reconfiguration for improved hardware utilization.

This seminar will be online on Zoom: https://utoronto.zoom.us/j/82613229697

This talk is part of the CAS Talks series.

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• https://utoronto.zoom.us/j/82613229697
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