Modular SRAM-based Binary Content-Addressable Memories

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• Ameer Abdelhadi (Imperial College)
• Monday 14 January 2019, 16:00-17:00
• Level 9 Seminar Room, EEE Dept..

If you have a question about this talk, please contact George A Constantinides.

Binary Content Addressable Memories (BCAMs), also known as associative memories, are hardware-based search engines. BCA Ms employ a massively parallel exhaustive search of the entire memory space, and are capable of matching a specific data within a single cycle. Networking, memory management, pattern matching, data compression, DSP , and other applications utilize CAMs as single-cycle associative search accelerators. Due to the increasing amount of processed information, modern BCAM applications demand a deep searching space. However, traditional BCAM approaches in FPG As suffer from storage inefficiency. In this paper, a novel, efficient and modular technique for constructing BCA Ms out of standard SRAM blocks in FPG As is proposed. Hierarchical search is employed to achieve high storage efficiency. Previous hierarchical search approaches cannot be cascaded since they provide a single matching address; this incurs an exponential increase of RAM consumption as pattern width increases. Our approach, however, efficiently regenerates a match indicator for every single address by storing indirect indices for address match indicators. Hence, the proposed method can be cascaded and exponential growth is alleviated into linear. Our method exhibits high storage efficiency and is capable of implementing up to 9 times wider BCA Ms compared to other approaches. A fully parameterized Verilog implementation is being released as an open source library. The library has been extensively tested using Altera’s Quartus and ModelSim.

This talk is part of the CAS Talks series.

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