Design and Optimization for Energy-Efficient Fault-Tolerant Systems

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• Rong Ye (Imperial College)
• Monday 28 July 2014, 11:00-12:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact Grigorios Mingas.

Over the past four decades, the number of transistors on a chip has increased exponentially in accordance with Moore’s law. Albeit the relentless scaling of CMOS technology has brought digital IC designs with enhanced functionality and improved performance in every new generation, the impediments to growth are more formidable today than ever before.

One of the largest barriers, on the one hand, is related to energy and power dissipation. It is not exaggerated that developing energy-efficient solutions is critical to the survival of the semiconductor industry. The emergency of energy/power reduction has motivated numerous low-power techniques spanning from circuit level up to system level to achieve energy efficiency. On the other hand, the associated ever-increasing on-chip power and temperature densities make IC designs suffer from severe reliability threats. As transistor size quickly reaches its physical limit, transistor behavior becomes even probabilistic rather than deterministic. It is generally believed that, the “CMOS endpoint” is approaching when CMOS transistor falls into the realm of quantum physics sooner or later.

In this talk, we are going to discuss the potential solutions for future energy-efficient fault-tolerant systems. Timing speculation (TS) is a novel error-resilient technique that is able to detect and correct timing violations on-the-fly and trade off reliability with power/performance. In addition, approximate computing (AC) has been emerging recently as a promising alternative to exploit the inherent error tolerance of error-resilient applications (e.g., multimedia) and trade off computation quality (e.g., accuracy) with computational effort (e.g., power).

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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