Designing optimal digital hardware using the Polytope Model

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• Samuel Bayliss (Imperial College)
• Thursday 20 October 2011, 13:00-14:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact Grigorios Mingas.

Mapping computation directly to hardware can enable performance improvements by exploiting parallelism. Loop nests within imperative programs are an obvious target area when searching for parallelism.

The Polytope Model is a mathematical abstraction for describing loop nests that allows reasoning about loop transformations and, through recent mathematical advances (notably polynomial time algorithms for counting the number of points within a polytope), allows one to evaluate the performance impact of transformations analytically.

This talk will introduce the polyhedral model, discuss recent work on loop transformations to improve SDRAM efficiency and describe a new backend tool for generating efficient digital hardware from polyhedral descriptions.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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