Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods

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• David P Boland (Imperial College)
• Thursday 29 October 2009, 13:00-14:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact George A Constantinides.

Accelerating iterative methods using FPG As has previously been studied in detail within this research group, with large performance improvements achieved over general purpose processors. In these works, this performance gain is largely a result of parallelisation of the matrix-vector multiplication; parallelism that mainly results from taking advantage of the nature of iterative methods which allow the use of on-chip memory buffers to increase the bandwidth. Unfortunately, the RAM available on FPG As has limited this high performance to only relatively small matrices. This work examines simple hardware changes that take advantage of symmetrical and banded matrix structure, as well as methods to optimise the RAM use in order to both increase the performance and retain this performance for larger order matrices.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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