Imperial College London > Talks@ee.imperial > CAS Talks > Formal Verification of High-Level Synthesis
Log inImperial users Other users No account?Information onFinding a talk Adding a talk Syndicating talks Who we are Everything else |
Formal Verification of High-Level SynthesisAdd to your list(s) Download to your calendar using vCal
If you have a question about this talk, please contact George A Constantinides. High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language like Verilog, while maintaining the convenience and the rich ecosystem of software development. However, current HLS tools cannot always guarantee that the hardware designs they produce are equivalent to the software they were given, thus undermining any reasoning conducted at the software level. Worse, there is mounting evidence that existing HLS tools are actually quite unreliable, sometimes generating wrong hardware or crashing when given valid inputs.
This talk is part of the CAS Talks series. This talk is included in these lists:Note that ex-directory lists are not shown. |
Other listsType the title of a new list here Powertalk COMMSP & CP listOther talks |