TPU V4 and Trends in Accelerator Hardware

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• Mike Hutton (Google)
• Tuesday 26 September 2023, 14:00-15:00
• Online - see abstract.

If you have a question about this talk, please contact George A Constantinides.

This talk is part of the SpatialML seminar series and will be online at https://utoronto.zoom.us/j/82613229697

In this talk I will overview the evolution of the Tensor Processor Unit (TPU) to its 4th generation, including both the hardware architecture and the surrounding system. Of particular interest in this generation is optical switching to scale the system to thousands of worker-chips while maintaining reliability against individual system downtime. Then I will give a view of the architecture definition process and how the performance is modeled during development and some of the trends in ML workloads that are influencing the design of future accelerator systems.

Mike Hutton received his BMath in Computer Science in 1989 and MMath in Computer Science in 1991, both from the University of Waterloo, and his Ph.D. in Computer Science in 1997 from the University of Toronto. Across 20 years at Altera, Tabula and Intel, he worked on FPGA architecture, CAD and applications. He is author of 30 published papers and 100+ US patents in these areas, has served on multiple FPGA and CAD program committees, and is a former Associate Editor for IEEE Transactions on VLSI . In 2018 he joined Google and is focused on architecture and performance modeling for the Tensor Processor (TPU) architecture.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Online - see abstract

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