Imperial College London > Talks@ee.imperial > CAS Talks > ARC2010: A Fused Hybrid Floating-Point and Fixed-Point Dot-product for FPGAs

ARC2010: A Fused Hybrid Floating-Point and Fixed-Point Dot-product for FPGAs

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  • UserAntonio Roldao Lopes (PhD at IC)
  • ClockWednesday 03 March 2010, 13:30-14:00
  • HouseRoom 503/EEE.

If you have a question about this talk, please contact George A Constantinides.

Dot-products are one of the essential and recurrent building blocks in scientific computing, and often take-up a large proportion of the scientific acceleration circuitry. The acceleration of dot-products is very well suited for Field Programmable Gate Arrays (FPGAs) since these devices can be configured to employ wide parallelism, deep pipelining and exploit highly efficient datapaths. In this paper we present a dot- product implementation which operates using a hybrid floating-point and fixed-point number system. This design receives floating-point in- puts, and generates a floating-point output. Internally it makes use of a configurable word-length fixed-point number system. The internal rep- resentation can be tuned to match the desired accuracy. Results using a high-end Xilinx FPGA and an order 150 dot-product demonstrate that, for equivalent accuracy metrics, it is possible to utilize 3.8 times fewer resources, operate at 1.62 times faster clock frequency, and achieve a significant reduction in latency when compared to a direct floating-point core based dot-product. Combining these results and utilizing the spare resources to instantiate more units in parallel, it is possible to achieve an overall speed-up of at least 5 times.

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