Shared Virtual Memory in Heterogeneous Systems

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• Felix Winterstein (Imperial College)
• Monday 12 June 2017, 15:00-16:00
• Level 9 Seminar Room, EE Dept..

If you have a question about this talk, please contact George A Constantinides.

Heterogeneous CPU -FPGA systems are gaining momentum in the embedded systems sector (for example Xilinx Zynq and Intel’s Cyclone V SoC) and in the data center market (for example Intel’s Xeon-FPGA hybrid). My current research seeks to develop and benchmark advanced high-level compilation techniques which automatically implement application-specific optimisations of the memory and communication sub-system in tightly coupled CPU -FPGA systems. It focuses on programming environments providing a virtual memory space which is shared between the host CPU and one (or potentially several) FPGA accelerators. One example of shared virtual memory (SVM) is defined by the recent OpenCL 2.0 standard, which is currently gaining increasing popularity in the FPGA community. SVM abstracts away the low-level details of the communication between the physical memory spaces of the host and the accelerator; it allows the software and hardware portion of a hybrid application to seamlessly (and concurrently) share complex data structures, which greatly eases the programming heterogeneous systems. In this talk, I will describe the physical infrastructure underneath the high-level view of a unified virtual address space that I have developed during the last months. This includes an example of integrating custom RTL code in OpenCL kernels. I will also discuss the customisation of the underlying physical memory and communication architecture according to the specific requirements of the application. Thirdly, I will give an outlook of how these techniques can be applied in the Broadwell+FPGA prototype system, to which we have been given access within the scope of Intel’s Hardware Accelerator Research Program (HARP).

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EE Dept.

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