Fault recovery through dynamic partial reconfiguration in FPGA-based systems and TMR as a protection method from SEUs in FPGAs

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• Michail Vavouras (Imperial College London)
• Wednesday 10 April 2013, 11:00-12:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact Grigorios Mingas.

In this talk the work that has been done for bypassing faulty components of an application mapped on an FPGA by using dynamic partial reconfiguration will be presented. Two case studies have been studied: a second order polynomial IP and an artificial pancreas IP. Moreover, a technique for partial bitstream relocation will be presented as a way of avoiding faults in the reconfigurable partitions.

Preliminary work towards protecting arithmetic operators (Adder)from Single Event Upsets (SEUs) in FPG As will be also discussed.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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