Improving FPGA reliability with wear-levelling (FPL practice)

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• Ed Stott, CAS Group
• Tuesday 23 August 2011, 10:00-11:00
• Level 9 Mahanakorn Lab., EE Dept..

If you have a question about this talk, please contact Wiesia R Hsissen.

As VLSI circuits achieve smaller geometries, reliability is becoming a growing problem. The flexibility of FPG As enables novel techniques for meeting this challenge, and one such technique is wear-levelling: periodic reconfiguration to eliminate electrical stress hotspots. In this work we have carried out accelerated-life experiments on FPG As to assess the feasibility of three wear-levelling strategies for reducing timing degradation. All three techniques resulted in significant improvements to robustness compared with a static configuration, and we have demonstrated that wear-levelling is a promising tool for improving FPGA reliability.

This talk is part of the CAS Talks series.

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• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EE Dept.

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