Modulo Scheduling in Electronic System Level Synthesis - Improving Performance and Control

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• Patrick Sittel (U Kassel, Germany)
• Monday 18 March 2019, 16:00-17:00
• Denis Gabor Seminar Room, 611.

If you have a question about this talk, please contact John Wickerson.

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The accessibility of FPG As in mainstream computing is linked to the quality of available tool flows and the performance of generated hardware.

This talk will focus on two novel approaches that improve on state-of-the-art methods regarding the automated generation of high-throughput / low area FPGA implementations.

1) Multi-objective Resource-aware Modulo Scheduling (under review) 2) Rational II Modulo Scheduling (to be submitted)

This talk is part of the CAS Talks series.

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• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Denis Gabor Seminar Room, 611

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