EASY: Efficient Arbiter SYnthesis from Multi-threaded Code

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• Jianyi Cheng (Imperial College)
• Monday 04 February 2019, 16:00-17:00
• Level 9 Seminar Room, EEE Dept..

If you have a question about this talk, please contact George A Constantinides.

This is a practice presentation for FPGA 2019 (Round 2)

High-Level Synthesis (HLS) tools automatically transform a high-level specification of a circuit into a low-level RTL description. Traditionally, HLS tools have operated on sequential code, however in recent years there has been a drive to synthesize multi-threaded code. A major challenge facing HLS tools in this context is how to automatically partition memory amongst parallel threads to fully exploit the bandwidth available on an FPGA device and avoid memory contention. Current automatic memory partitioning techniques have inefficient arbitration due to conservative assumptions regarding which threads may access a given memory bank.

In this paper, we address this problem through formal verification techniques, permitting a less conservative, yet provably correct circuit to be generated.

We perform a static analysis on the code to determine which memory banks are shared by which threads. This analysis enables us to optimize the arbitration efficiency of the generated circuit. We apply our approach to the LegUp HLS tool and show that for a set of typical application benchmarks we can achieve up to 87% area savings, and 39% execution time improvement, with little additional compilation time.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Seminar Room, EEE Dept.

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