High Performance FPGA Design

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• Martin Langhammer (Intel and Imperial)
• Monday 29 January 2024, 13:00-14:00
• Department of Electrical and Electronic Engineering, Room 909B.

If you have a question about this talk, please contact George A Constantinides.

This talk is about high speed AND high density. How to get close to 1GHz in current FPG As, not by hammering the tools (which doesn’t work), but by making your architecture fit the FPGA . Will also cover high speed/wide datapath data transfers, and how routing in the FPGA can be used for both high speed design and high speed/wide datapath data transfer – all at the same time.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Department of Electrical and Electronic Engineering, Room 909B

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