Timing Fault Detection in FPGAs

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• Edward A Stott (Imperial College)
• Wednesday 29 January 2014, 11:00-12:00
• Level 9 Mahanakorn Lab., EEE Dept..

If you have a question about this talk, please contact Grigorios Mingas.

The operation of FPGA systems is traditionally governed by static timing analysis, whereby safety margins for operating and manufacturing uncertainty are factored in at design-time. If we operate FPGA designs beyond these conservative margins we can obtain substantial energy and performance improvements. Doing so, however, introduces a risk of timing faults.

In this talk I present a system for detecting timing faults in arbitrary FPGA circuits based on Razor-like shadow register insertion. Through a combination of calibration, timing constraint and adaptation of the CAD flow, we deliver low-overhead, trustworthy fault detection for FPGA -based circuits. We use the technique to establish to potential benefits of low-level timing fault correction in a range of common numerical applications.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EEE Dept.

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