Asynchronous circuits for High-performance Energy Minimum Operation

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• Ben Devlin, University of Tokyo
• Friday 09 December 2011, 13:00-14:00
• Level 9 Mahanakorn Lab., EEE Dept..

If you have a question about this talk, please contact Wiesia R Hsissen.

Asynchronous architectures allow for delay-insensitive operation by removing the global clock signal found in synchronous circuits, and replacing it with completion detection circuits that automatically adapt to the flow of data. As voltage supply is reduced in order to achieve energy minimum operation, asynchronous circuits show performance advantages over synchronous circuits because of the automatic adaption to the flow of data, providing robustness to process, voltage, and temperature (PVT) variations that are present in low voltage operation. We have researched and designed a asynchronous FPGA (SSFPGA) which uses a combination of autonomous power gating and low voltage operation to achieve energy minimum operation. A 65nm SSFPGA is fabricated and shows operation from 0.37V to 1.6V, with energy minimum operation at 0.6V of 17fJ/operation, while operating at 264MHz.

This talk is part of the CAS Talks series.

This talk is included in these lists:

• Andrea Picciau's list
• CAS Talks
• Circuits and Systems Group: Internal Seminars
• Level 9 Mahanakorn Lab., EEE Dept.

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